TLV3901 features an integrated latch function for holding the CML outputs in a fixed state. CML input pins Latch Enable (LE) and Latch Enable Bar (LEB) control the latch functionality and the pins are internally terminated with 50Ω to VCCO. When LE is high (VCCO) and LEB is low (VCCO-1), the comparator output is latched.

An important consideration of the latch functionality is the latch hold time. Latch hold time is the minimum time after latch mode is asserted for properly latching the comparator output. Likewise, latch setup time is defined as the time that the input must be stable before the latch mode is asserted. The figure below illustrates when LE and LEB can transition for a valid latch.

Figure 6-3 Valid Latch Diagram

A small delay (tPL) in the output response is shown below when the TLV3901 exits a latched output state.

Figure 6-4 Latch Disable with Input Change

Latch mode is disabled by connecting LE to a voltage that is a minimum of 200mV below VCCO, while LEB is left unconnected (floating). Note that the acceptable range for either LE or LEB is VCCO to VCCO - 1V with a minimum difference voltage of 200mV.