SNOSDK7A
October 2025 – December 2025
TLV3901
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Latching/Adjustable Hysteresis
5.8
Timing Diagrams
5.9
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.4
Device Functional Modes
6.4.1
Inputs
6.4.2
CML Output
6.4.3
Latch Functionality
6.4.4
Adjustable Hysteresis
7
Application and Implementation
7.1
Application Information
7.1.1
Application Overview
7.2
Typical Application
7.2.1
Optical Receiver
7.2.1.1
Design Requirements
7.2.1.2
Detailed Design Procedure
7.2.1.3
Application Performance Plots
7.2.2
External Trigger Function for Oscilloscopes
7.2.3
Logic Clock Source to CML Transceiver
7.3
Power Supply Recommendations
7.4
Layout
7.4.1
Layout Guidelines
7.4.2
Layout Example
8
Device and Documentation Support
8.1
Device Support
8.1.1
Related Documentation
8.2
Receiving Notification of Documentation Updates
8.3
Support Resources
8.4
Trademarks
8.5
Electrostatic Discharge Caution
8.6
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
1
Features
Low propagation delay: 125ps
Low overdrive dispersion: 5ps
Quiescent current: 53mA
High toggle frequency: 10GHz / 20Gbps
Narrow pulse width detection capability: 60ps
CML output
Separate input and output supplies
Single supply voltage: 3.1V to 5.25V
Low input offset voltage: ±1mV
On-chip terminations at both input pins
Resistor programmable hysteresis
Differential latch control