SNVA866A February   2019  – January 2023 LM5155 , LM5155-Q1 , LM51551 , LM51551-Q1

 

  1.   How to design an Isolated Flyback using LM5155
  2.   Trademarks
  3. 1Introduction
  4. 2Example Application
  5. 3Calculations and Component Selection
    1. 3.1 Switching Frequency
    2. 3.2 Transformer Selection
      1. 3.2.1 Maximum Duty Cycle and Turns Ratio Selection
      2. 3.2.2 Primary Winding Inductance Selection
    3. 3.3 Current Sense Resistor Calculations
      1. 3.3.1 Current Sense Resistor and Slope Compensation Resistor Selection
      2. 3.3.2 Current Sense Resistor Filter Selection
    4. 3.4 MOSFET Selection
    5. 3.5 Diode Selection
    6. 3.6 Output Capacitor Selection
    7. 3.7 Input Capacitor Selection
    8. 3.8 UVLO Resistor Selection
    9. 3.9 Control Loop Compensation
      1. 3.9.1 Feedback Resistor Selection
      2. 3.9.2 RPULLUP Selection
      3. 3.9.3 Optocoupler Selection
      4. 3.9.4 RLED Selection
      5. 3.9.5 Crossover Frequency Selection
      6. 3.9.6 Determine Required RCOMP
      7. 3.9.7 Determine Required CCOMP
  6. 4Component Selection Summary
  7. 5Small Signal Frequency Analysis
    1. 5.1 Flyback Regulator Modulator Modeling
    2. 5.2 Compensation Modeling
  8. 6Revision History

3.4 MOSFET Selection

MOSFET selection for a flyback controller focuses on power dissipation and voltage rating. Power dissipation of MOSFET is composed of two different parts, conduction losses and switching losses. Conduction losses are dominated by the RDS(ON) resistance of the MOSFET. Switching losses occur during the rise time and fall time of the switch node, when the N-channel MOSFET is turning on and turning off. During the rise time and fall time, current through the MOSFET channel and a large voltage drop across the drain to source are present, resulting in power dissipation. The longer the rise and fall time of the switch node the higher the switching losses. Selecting a MOSFET with minimal parasitic capacitances decreases the switching losses.

The total gate charge (QG_total) must be small enough to keep the internal VCC regulator from entering current limit. The QG_total for a given MOSFET can be found in the component data sheet. Equation 16 provides the maximum total gate charge of the MOSFET for the selected switching frequency. The QG_total of the selected MOSFET is 35nC.

Equation 16. GUID-BEE13B4D-18B5-45B3-B8CF-485E18C362F5-low.gif

The RMS current of the MOSFET is estimated using Equation 17. By estimating the switch RMS current, a MOSFET with an adequately small RDS(ON) value is selected.

Equation 17. GUID-01F94C7B-6854-4045-9F94-96E422B789FD-low.gif

The RDS(ON) of the selected MOSFET is 8.7mΩ.

The drain to source break down voltage rating on the MOSFET needs to be higher than the reflected secondary side voltage plus the maximum input voltage as calculated in Equation 18.

Equation 18. GUID-22E25C74-7879-4801-8532-55611495523F-low.gif

Due to the parasitic leakage inductance of the primary winding, the switch node voltage rings well above the value calculated in Equation 18. To overcome the ringing on the switch node a voltage clamp can be added. Designing this clamp is not described in this application report. For this design a MOSFET with a voltage rating of 100 V is selected.