SNVAA63 March   2023 TPSM365R6

 

  1.   Abstract
  2.   Trademarks
  3. 1Inverting Buck-Boost Topology
    1. 1.1 Concept
    2. 1.2 Output Current Calculations
    3. 1.3 VIN and VOUT Range in Inverting Configuration
  4. 2Design Considerations
    1. 2.1 Additional Bypass Capacitor and Schottky Diode
    2. 2.2 Start-up Behavior and Switching Node Consideration
  5. 3External Components
    1. 3.1 Capacitor Selection
    2. 3.2 System Loop Stability
  6. 4Typical Performance
  7. 5Digital Pin Configurations
    1. 5.1 Digital Input Pin
    2. 5.2 Power-Good Pin
  8. 6Conclusion
  9. 7References

Digital Input Pin

The TPSM365R6 has a digital input pin (EN) that can be used to turn the output of the device on and off. In the TPSM365R6 buck configuration, the specified typical threshold voltages for the EN pin with respect to TPSM365R6 IC GND is considered high above 1.36 V and low below 0.4 V. However, in the inverting buck-boost configuration, EN is now referenced to –VOUT voltage, not the TPSM365R6 IC GND; therefore, the threshold for the EN pin to be considered high is 1.36 V + –VOUT, and the threshold for the EN pin to be considered low is 0.4 V + -VOUT. For example, if –VOUT = –12 V, EN will be considered high for voltages above –10.64 V and low for voltages below –11.6 V. Thus, at startup a negative output voltage will cause EN to turn on, but will require a voltage of at least 0.4 V + –VOUT to shutdown the device. This behavior can cause difficulties disabling the part, because in many applications the voltage rail supplying the EN signal will not be able to produce the negative voltage required to turn EN low.

A relatively simple level shifter can alleviate any problems associated with the EN threshold voltages by eliminating the need for negative EN signals. Figure 5-1 shows the required connections to create the EN pin level shifter.

Figure 5-1 EN Pin Level Shifter
Table 5-1 Logic States with EN Level Shifter
SYS_EN LOW HIGH
Q1 OFF ON
Q2 OFF ON
EN Pin LOW HIGH

The positive signal (SYS_EN) that originally drove EN is now tied to the gate of Q1 in this level shifter. When SYS_EN is set to SYS_GND, Q1 turns off. Subsequently, Q2 detects no potential difference between its gate and source and also remains off. In this state, the EN pin detects -VOUT, which is below the low level threshold and disables the device.

When SYS_EN provides enough positive voltage to between Q1's gate and source to turn Q1 on, the gate of Q2 is pulled to SYS_GND through Q1. This drives a negative potential difference between Q2's gate and source, turning it on. Consequently, EN is tied to VIN through Q2, and the pin is above the high level threshold, causing the device to turn on.

It is important to select Q2 MOSFETs with the proper voltage ratings for the expected application conditions. Additional Zener diodes and/or a resistor divider can be used to lower the potential of Q2's gate. Ensure that the Q2 limits found in the MOSFET's data sheet are adhered to in both the on and off states of the IC.

The SYS_EN signal activates the EN pin level shifter circuit and swings the EN pin voltage to VIN and -VOUT, properly enabling and disabling the device. Figure 5-2 and Figure 5-3 show the behavior of the device with the EN pin level shifter installed.

Figure 5-2 EN Pin Level Shifter on Start-Up
Figure 5-3 EN Pin Level Shifter on Shutdown