SNVAAB4 January   2026 LM63615-Q1 , LM63625-Q1 , LM63635-Q1

 

  1.   1
  2.   Summary
  3. 1 Profile
  4. 2 Generation of the reverse current
  5. 3 EOS failure case
  6. 4 Potential cause
  7. 5 EVM test
  8. 6 Reverse current generation and failure process
  9. 7 Data validation
  10. 8 Design recommendations
  11. 9 Summary
  12. 10References:

6 Reverse current generation and failure process

In the above text, the above tests conducted through the EVM find that there is indeed a large reverse current in the current application. While the chip on EVM is not damaged, large sample sizes can significantly increase the risk of breakdown due to reverse current. This chapter details how reverse current causes instantaneous failure during the switching process of a buck converter, along with the complete failure sequence.

(1) Q1 turn-on and dead-time phase

Q1 turn-on and dead-time phaseFigure 6-1 Q1 turn-on and dead-time phase

At power down or when the input falls below the output, the reverse current path is VOUT-> SW-> Q1 body diode-> VIN. During this phase, Cds is charged.

  • When the upper transistor Q1 turns on, the lower transistor Q2 turns off, Cds is charged and the reverse current flows to VIN;
  • When the upper transistor Q1 turns off, the lower transistor Q2 turns on and a reverse current flows from the lower transistor into GND for discharging.
  • During the dead time, reverse current flows towards VIN via the body diode of upper transistor Q1, whilst Cds is simultaneously charged.

(2) Phase at which Q1 turns off and Q2 turns on

Phase at which Q1 turns off and Q2 turns onFigure 6-2 Phase at which Q1 turns off and Q2 turns on

When upper transistor Q1 turns off and lower transistor Q2 turns on:

  • At this point, in addition to the reverse current of the output;
  • Cds charged during Q1 turn-on phase and dead-time phase simultaneously discharges through the lower transistor;
  • Reverse recovery current from the body diode conducting during dead time is also discharged by the lower transistor conduction.

Generally, the turn-on time of the lower transistor is at ns level. Consequently, calculations indicate that even with reverse currents of merely several hundred mA, di/dt variation becomes substantial enough to reach levels capable of damaging the lower transistor MOSFET.

(3) Failure process analysis

Lower transistor failureFigure 6-3 Lower transistor failure
  • PIN12: Due to substantial di/dt, the lower transistor MOSFET fails, manifesting as a short circuit. Following the rapid connection of VOUT to GND, the output drops sharply. At this point, the upper transistor conducts, causing VIN to be directly shorted to GND. The resulting massive short-circuit current directly burns through VIN bonding wire on DIE, resulting in the failure symptom where VIN is displayed as OPEN.
  • PIN3: VCC is an internal LDO PIN directly sourcing power from VIN to buck for internal logic supply. A VIN short-circuit device's immense current breaks down the internal LDO, causing VCC short-circuit.
  • PIN1: SW exhibits failure as a short to GND due to the lower transistor short-circuit.

Additionally, some failures manifest as BOOT PIN short-circuits. This can be explained by the substantial di/dt simultaneously creating Figure 6-4 a significant potential difference across the BOOT capacitor. When this potential difference exceeds the breakdown voltage of BOOT capacitor, it forms a short-circuit loop with VCC breakdown.

BOOT failureFigure 6-4 BOOT failure

(4) Other issues

Depending on the failure process of the reverse current, the following questions may arise:

  • Why does the failure case only appear in PFM mode?

AUTO Mode (PFM Mode): Under light load, the chip reduces switching frequency to minimize switching and conduction losses, thereby lowering power consumption.

FPWM Mode: The chip maintains a constant switching frequency set by RT throughout operation, and it is currently designed to be 2.1MHz.

The charge accumulation in Cds during Q1 conduction is determined by the charging duration. This charging time of Cds comprises Q1 conduction and dead time, with the latter being fixed. Consequently, the primary influencing factor is Q1's conduction time. Therefore, under light load conditions, the frequency is lower, resulting in a shorter discharge time for Q2 when it turns on. If the discharge time for the reverse recovery current of the Cds and diode is too short, it will generate a substantial di/dt within a short period.

In summary, when the chip operates under light load conditions, a lower switching frequency results in a longer cycle time. Ton duration becomes longer compared to lower frequencies, meaning the upper transistor remains switched on for a longer period. This prolongs the charging time of the parasitic capacitances Cds and Cboot, leading to a greater current surge when the lower transistor switches on.

  • Why is it prone to appearing in the design of POC?

The same power board in this case also utilizes 2pcs of LM63635-Q1 devices, though their outputs are set to 3.9V/3.3V, without any failure issues observed. For POC power supply applications, outputs are often set to 8V. Automotive batteries typically operate within a 9-16V range, with some requiring 6-16V. When the automotive battery voltage is inherently low, reverse current is more readily induced on the 3.3V/3.9V/5V power rails during power-down. In the current case, the camera load is relatively light. Compared to 3.9V load on the other LM63635-Q1 on the board, it is more prone to entering PFM Mode, thereby further increasing the probability of reverse current breakdown.