SNVSA77D December   2015  – November 2016 LP5912

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Voltage Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Output and Input Capacitors
  8. 8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Enable (EN)
      2. 9.3.2 Output Automatic Discharge (RAD)
      3. 9.3.3 Reverse Current Protection (IRO)
      4. 9.3.4 Internal Current Limit (ISC)
      5. 9.3.5 Thermal Overload Protection (TSD)
      6. 9.3.6 Power-Good Output (PG)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Enable (EN)
      2. 9.4.2 Minimum Operating Input Voltage (VIN)
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 External Capacitors
        2. 10.2.2.2 Input Capacitor
        3. 10.2.2.3 Output Capacitor
        4. 10.2.2.4 Capacitor Characteristics
        5. 10.2.2.5 Remote Capacitor Operation
        6. 10.2.2.6 Power Dissipation
        7. 10.2.2.7 Estimating Junction Temperature
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VIN Input voltage –0.3 7 V
VOUT Output voltage –0.3 7 V
VEN Enable input voltage -0.3 7 V
VPG Power Good (PG) pin OFF voltage –0.3 7 V
TJ Junction temperature 150 °C
PD Continuous power dissipation(3) Internally Limited W
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the GND pin.
(3) Internal thermal shutdown circuitry protects the device from permanent damage.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process..
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN Input supply voltage 1.6 6.5 V
VOUT Output voltage 0.8 5.5
VEN Enable input voltage 0 VIN
VPG PG pin OFF voltage 0 6.5
IOUT Output current 0 500 mA
TJ-MAX-OP Operating junction temperature(2) –40 125 °C
(1) All voltages are with respect to the GND pin.
(2) TJ-MAX-OP = (TA(MAX) + (PD(MAX) × RθJA )).

7.4 Thermal Information

THERMAL METRIC(1) LP5912 UNIT
DRV (WSON)
6 PINS
RθJA Junction-to-ambient thermal resistance, High-K(2) 71.2(3) °C/W
RθJC(top) Junction-to-case (top) thermal resistance 93.7 °C/W
RθJB Junction-to-board thermal resistance 40.7 °C/W
ψJT Junction-to-top characterization parameter 2.5 °C/W
ψJB Junction-to-board characterization parameter 41.1 °C/W
RJC(bot) Junction-to-case (bottom) thermal resistance 11.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
(3) The PCB for the WSON (DRV) package RθJA includes two (2) thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5.

7.5 Electrical Characteristics

VIN = VOUT(NOM) + 0.5 V or 1.6 V, whichever is greater; VEN = 1.3 V, CIN = 1 µF, COUT = 1 µF, IOUT = 1 mA (unless otherwise stated).(1)(2)(3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT VOLTAGE
ΔVOUT Output voltage tolerance For VOUT(NOM) ≥ 3.3 V:
VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V,
IOUT = 1 mA to 500 mA 		–2% 2%
For 1.1 V ≤ VOUT(NOM) < 3.3 V:
VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V,
IOUT = 1 mA to 500 mA 		–3% 3%
For VOUT(NOM) < 1.1 V:
1.6 V ≤ VIN ≤ 6.5 V,
IOUT = 1 mA to 500 mA
Line regulation For VOUT(NOM) ≥ 1.1V:
VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V		 0.8 %/V
For VOUT(NOM) < 1.1V :
1.6 V ≤ VIN ≤ 6.5 V
Load regulation IOUT = 1 mA to 500 mA 0.0022 %/mA
CURRENT LEVELS
ISC Short-circuit current limit TJ = 25°C, see(4) 700 900 1100 mA
IRO Reverse leakage current(5) VEN = VIN = 0 V, VOUT = 5.5 V 10 150 µA
IQ Quiescent current(6) VEN = 1.3 V, IOUT = 0 mA 30 55 µA
VEN = 1.3 V, IOUT = 500 mA 400 600
IQ(SD) Quiescent current, shutdown mode(6) VEN = 0 V
–40°C ≤ TJ ≤ 85°C		 0.2 1.5 µA
VEN = 0 V
 0.2 5
IG Ground current(7) VEN = 1.3 V, IOUT = 0 mA 35 µA
VDO DROPOUT VOLTAGE
VDO Dropout voltage(8) IOUT = 500 mA, 1.6 V ≤ VOUT(NOM) < 3.3 V 170 250 mV
IOUT = 500 mA, 3.3 V ≤ VOUT(NOM) ≤ 5.5 V 95 180 mV
VIN to VOUT RIPPLE REJECTION
PSRR Power Supply Rejection Ratio(10) ƒ = 100 Hz, VOUT ≥ 1.1 V, IOUT = 20 mA 80 dB
ƒ = 1 kHz, VOUT ≥ 1.1 V, IOUT = 20 mA 75
ƒ = 10 kHz, VOUT ≥ 1.1 V, IOUT = 20 mA 65
ƒ = 100 kHz, VOUT ≥ 1.1 V, IOUT = 20 mA 40
ƒ = 100 Hz, 0.8 V < VOUT < 1.1 V, IOUT = 20 mA 65
ƒ = 1 kHz, 0.8 V < VOUT < 1.1 V, IOUT = 20 mA 65
ƒ = 10 kHz, 0.8 V < VOUT < 1.1 V, IOUT = 20 mA 65
ƒ = 100 kHz, 0.8 V < VOUT < 1.1 V, IOUT = 20 mA 40
OUTPUT NOISE VOLTAGE
eN Noise voltage IOUT = 1 mA, BW = 10 Hz to 100 kHz 12 µVRMS
IOUT = 500 mA, BW = 10 Hz to 100 kHz 12
THERMAL SHUTDOWN
TSD Thermal shutdown temperature 160 °C
THYS Thermal shutdown hysteresis 15 °C
LOGIC INPUT THRESHOLDS
VEN(OFF) OFF Threshold VIN = 1.6 V to 6.5 V
VEN falling until device is disabled		 0.3 V
VEN(ON) ON Threshold 1.6 V ≤ VIN ≤ 6.5 V
VEN rising until device is enabled		 1.3
IEN Input current at EN pin(9) VEN = 6.5 V, VIN = 6.5 V 2.5 µA
VEN = 0 V, VIN = 3.3 V 0.001
PGHTH PG high threshold (% of nominal VOUT) 94%
PGLTH PG low threshold (% of nominal VOUT) 90%
VOL(PG) PG pin low-level output voltage VOUT < PGLTH, sink current = 1 mA 100 mV
IlKG(PG) PG pin leakage current VOUT < PGHTH, VPG = 6.5 V 1 µA
tPGD PG delay time Time from VOUT > PG threshold to PG toggling 140 µs
TRANSITION CHARACTERISTICS
ΔVOUT Line transients(10) For VIN ↑ and VOUT(NOM) ≥ 1.1 V:
VIN = (VOUT(NOM) + 0.5 V) to (VOUT(NOM) + 1.1 V)
VIN trise = 30 µs		 1 mV
For VIN ↑ and VOUT(NOM) < 1.1 V:
VIN = 1.6 V to 2.2 V
VIN trise = 30 µs
For VIN ↓ and VOUT(NOM) ≥ 1.1 V
VIN = (VOUT(NOM) + 1.1 V) to (VOUT(NOM) + 0.5 V)
VIN tfall = 30 µs		 –1
For VIN ↓ and VOUT(NOM) < 1.1 V:
VIN = 2.2 V to 1.6 V
VIN tfall = 30 µs
Load transients(10) IOUT = 5 mA to 500 mA
IOUT trise = 10 µs		 –45 mV
IOUT = 500 mA to 5 mA
IOUT tfall = 10 µs		 45
Overshoot on start-up(10) Stated as a percentage of VOUT(NOM) 5%
tON Turnon time Time from VEN > VEN(ON) to VOUT = 95% of VOUT(NOM) 200 µs
OUTPUT AUTO DISCHARGE RATE
RAD Output discharge pull-down resistance VEN = 0 V, VIN = 3.6 V 100 Ω
(1) All voltages are with respect to the device GND pin, unless otherwise stated.
(2) Minimum and maximum limits are ensured through test, design, or statistical correlation over the junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Typical values represent the most likely parametric norm at TA = 25°C, and are provided for reference purposes only.
(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
(4) Short-circuit current (ISC) is equivalent to current limit. To minimize thermal effects during testing, ISC is measured with VOUT pulled to 100 mV below its nominal voltage.
(5) Reverse current (IRO) is measured at the IN pin.
(6) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.
(7) Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device.
(8) Dropout voltage (VDO) is the voltage difference between the input and the output at which the output voltage drops to 150 mV below its nominal value when VIN = VOUT + 0.5 V. Dropout voltage is not a valid condition for output voltages less than 1.6 V as compliance with the minimum operating voltage requirement cannot be assured.
(9) There is a 3-MΩ pulldown resistor between the EN pin and GND pin on the device.
(10) This specification is ensured by design.

7.6 Output and Input Capacitors

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN(1) TYP MAX UNIT
CIN Input capacitance(2) Capacitance for stability 0.7 1 µF
COUT Output capacitance(2) 0.7 1 10 µF
ESR Output voltage(2) 5 500 mΩ
(1) The minimum capacitance must be greater than 0.5 μF over full range of operating conditions. The capacitor tolerance must be 30% or better over the full temperature range. The full range of operating conditions for the capacitor in the application must be considered during device selection to ensure this minimum capacitance specification is met. X7R capacitors are recommended however capacitor types X5R, Y5V, and Z5U may be used with consideration of the application conditions.
(2) This specification is verified by design.