SNVSAD7C June   2015  – December 2024 LV14340

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Fixed Frequency Peak Current Mode Control
      2. 6.3.2  Slope Compensation
      3. 6.3.3  Pulse Skipping Mode
      4. 6.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 6.3.5  Adjustable Output Voltage
      6. 6.3.6  Enable and Adjustable Undervoltage Lockout
      7. 6.3.7  External Soft Start
      8. 6.3.8  Switching Frequency and Synchronization (RT/SYNC)
      9. 6.3.9  Overcurrent and Short-Circuit Protection
      10. 6.3.10 Overvoltage Protection
      11. 6.3.11 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Active Mode
      3. 6.4.3 CCM Mode
      4. 6.4.4 Light Load Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Voltage Set-Point
        2. 7.2.2.2 Switching Frequency
        3. 7.2.2.3 Output Inductor Selection
        4. 7.2.2.4 Output Capacitor Selection
        5. 7.2.2.5 Schottky Diode Selection
        6. 7.2.2.6 Input Capacitor Selection
        7. 7.2.2.7 Bootstrap Capacitor Selection
        8. 7.2.2.8 Soft-start Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.2.4 Output Capacitor Selection

Take care choosing the output capacitor or capacitors, COUT because the output capacitor or capacitors directly affect the steady state output voltage ripple, loop stability, and the voltage overshoot and undershoot during load current transients.

The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the Equivalent Series Resistance (ESR) of the output capacitors:

Equation 12. LV14340

The other is caused by the inductor current ripple charging and discharging the output capacitors:

Equation 13. LV14340

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rate. When a fast large load increase happens, output capacitors provide the required charge before the inductor current can slew up to the appropriate level. The control loop of the regulator usually needs three or more clock cycles to respond to the output voltage droop. The output capacitance must be large enough to supply the current difference for three clock cycles to maintain the output voltage within the specified range. Equation 14 shows the minimum output capacitance needed for specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb energy stored in the inductor. The catch diode cannot sink current, so the energy stored in the inductor results in an output voltage overshoot. Equation 15 calculates the minimum capacitance required to keep the voltage overshoot within a specified range.

Equation 14. LV14340
Equation 15. LV14340

where

  • KIND = Ripple ratio of the inductor ripple current (ΔiL / IOUT)
  • IOL = Low level output current during load transient
  • IOH = High level output current during load transient
  • VUS = Target output voltage undershoot
  • VOS = Target output voltage overshoot

For this design example, the target output ripple is 50 mV. Assume ΔVOUT_ESR = ΔVOUT_C = 50 mV, and choose KIND = 0.4. Equation 12 yields ESR no larger than 35.7 mΩ and Equation 13 yields COUT no smaller than 7 μF. For the target overshoot and undershoot range of this design, VUS = VOS = 5% × VOUT = 250 mV. The COUT can be calculated to be no smaller than 75.6 μF and 30.8 μF by Equation 14 and Equation 15, respectively. In summary, the most stringent criteria for the output capacitor is 75.6 μF. Two 47 μF, 16 V, X7R ceramic capacitors with 5 mΩ ESR are used in parallel.