SNVSC55 September   2025 LM51770-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Gate Driver Rise Time and Fall Time
    2. 7.2 Gate Driver Dead (Transition) Time
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power-On Reset (POR System)
      2. 8.3.2  Buck-Boost Control Scheme
        1. 8.3.2.1 Boost Mode
        2. 8.3.2.2 Buck Mode
        3. 8.3.2.3 Buck-Boost Mode
      3. 8.3.3  Power Save Mode
      4. 8.3.4  Supply Voltage Selection – VMAX Switch
      5. 8.3.5  Enable and Undervoltage Lockout
      6. 8.3.6  Oscillator Frequency Selection
      7. 8.3.7  Frequency Synchronization
      8. 8.3.8  Voltage Regulation Loop
      9. 8.3.9  Output Voltage Tracking
      10. 8.3.10 Slope Compensation
      11. 8.3.11 Configurable Soft Start
      12. 8.3.12 Peak Current Sensor
      13. 8.3.13 Current Monitoring and Current Limit Control Loop
      14. 8.3.14 Short Circuit - Hiccup Protection
      15. 8.3.15 nFLT Pin and Protections
      16. 8.3.16 Device Configuration Pin
      17. 8.3.17 Dual Random Spread Spectrum – DRSS
      18. 8.3.18 Gate Driver
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design with WEBENCH Tools
        2. 9.2.2.2  Frequency
        3. 9.2.2.3  Feedback Divider
        4. 9.2.2.4  Inductor and Current Sense Resistor Selection
        5. 9.2.2.5  Slope Compensation
        6. 9.2.2.6  Output Capacitor
        7. 9.2.2.7  Input Capacitor
        8. 9.2.2.8  UVLO Divider
        9. 9.2.2.9  Soft-Start Capacitor
        10. 9.2.2.10 MOSFETs QH1 and QL1
        11. 9.2.2.11 MOSFETs QH2 and QL2
        12. 9.2.2.12 Output Voltage Frequency Compensation
        13. 9.2.2.13 External Component Selection
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Bi-Directional Power Backup
      2. 9.3.2 Parallel (Multiphase) Operation
      3. 9.3.3 External Gate Driver with Logic Level High Side Gate Signals
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
        1. 9.5.1.1 Power Stage Layout
        2. 9.5.1.2 Gate Driver Layout
        3. 9.5.1.3 Controller Layout
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design with WEBENCH Tools
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1.     86

6.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise specified)(1)
MIN MAX UNIT
Input BIAS to AGND –0.3 50 V
Input VIN to AGND –0.3 85 V
Input UVLO/EN to AGND –0.3 V(VIN) + 0.3 V
Input ATRK/SS, DTRK, RT, SYNC, MODE, SLOPE, CFG, to AGND(2) –0.3 5.8 V
Input FB to AGND –0.3 5.8 V
Input CSA, CSB  to AGND(DC) –5 85 V
Input SW1, SW2  to AGND(DC) –5 85 V
Input HB1 to SW1, CSA, CSB –0.3 5.5(5) V
Input –0.3 6.4 V
Input HB2 to SW2, CSA, CSB –0.3 5.5(5) V
Input –0.3 6.4 V
Input SW1 to CSA, CSB –0.3 0.3 V
Input ISNSP to ISNSN –0.3 0.3 V
Input PGND to AGND –0.3 0.3 V
Output VCC to AGND –0.3 5.5 V
Output VOUT to AGND –0.3 85 V
Output LO1, LO2,  to AGND (DC) –5 V(VCC)+0.3 V
Output nFLT to AGND –0.3 5.8 V
Output
HO1 to SW1

–0.3 V(HB1) + 0.3 V
Output HO2 to SW2 –0.3 V(HB2) + 0.3 V
Output HO1, HO2, ISNSP, ISNSN, HB1, HB2  to AGND (DC) –0.3 85 V
Output COMP, IMONOUT to AGND(3) –0.3 5.8 V
Storage temperature, TSTG –55 150 °C
Operating junction temperature, TJ(4) –40 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) This pin is not specified to have an external voltage applied.
(3) This pin has an internal max voltage clamp which handles up to 1.6mA.
(4) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
(5) Operating lifetime is de-rated for voltage bigger than the specified maximum