SNVSCC2H November   2022  – April 2025 TPS389C03-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Maskable Interrupt (AMSK)
      3. 7.3.3  VDD
      4. 7.3.4  MON
      5. 7.3.5  NRST
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Packet Error Checking (PEC)
      9. 7.3.9  Q&A Watchdog
        1. 7.3.9.1 Question and Token Generation
        2. 7.3.9.2 Q&A Watchdog Open and Close Window Delay
        3. 7.3.9.3 Q&A Watchdog Status Register
        4. 7.3.9.4 Q&A Watchdog Timing
        5. 7.3.9.5 Q&A Watchdog State Machine and Test Program
      10. 7.3.10 Error Signal Monitoring (ESM)
        1. 7.3.10.1 ESM Timing
      11. 7.3.11 Register Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389C03-Q1 Power ON
  9. 8 Register Maps
    1. 8.1 Registers Overview
      1. 8.1.1 BANK0 Registers
      2. 8.1.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Guidelines
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Documentation Support
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

10.1 Device Nomenclature

Table 10-1 shows how to decode the function of the device based on the part number.

Table 10-1 Device Thresholds
ORDERING CODE Description
TPS389C0300CRTERQ1 3 Monitors, Q&A Watchdog, ESM
TPS389C03A26RTERQ1 3 Monitors, Q&A Watchdog, ESM
Table 10-2 TPS389C0300CRTERQ1 OTP Configuration

ADDR

DATA

Configuration Description

0x00

0x28

DEVICE_MODEL[7:3] and VENDOR_ID[2:0]

0x01

0x43

SILICON_REV[7:6] and OTP_REV[5:0]

0x02

0xF1

Channels disabled. MON2, 3, 4 enabled.

0x11

0x0C

WDO_DLY not applicable for latched WDO configuration
0x12 0x03 BIST at POR

0x13

0x06

Enable UVHF Mon2,3
0x14 0x06 Enable UVLF Mon2,3

0x15

0x06

Enable OVHF Mon2,3
0x16 0x06 Enable OVLF Mon2,3

0x1B

0x04

Thermal Shut Down Interrupt Enable
0x1C 0x01 Bist Fail Interrupt

0x1D

0x25

NRST MISMATCH, WDT → NIRQ, WDT → NRST, ESM → WDO not Mapped, ESM → NIRQ not Mapped, ESM → NRST not Mapped

0x1E

0x06

Enable Mon2,3

0x1F

0x06

Mon2,3 x4 Scaling

0x30

0xBC

4.56V UVHF Threshold Mon2

0x31

0xE8

5.44V OVHF Threshold Mon2
0x32 0xBC 4.56V UVLF Threshold Mon2
0x33 0xE8 5.44V OVLF Threshold Mon2

0x34

0xAA

102.4µs De-Bounce
0x35 0x1C O VHF → NRST, UVHF → NRST, 1kHz LF Cutoff

0x40

0x6F

3.02V UVHF Threshold Mon3

0x41

0x8C

3.6V OVHF Threshold Mon3
0x42 0x6F 3.02V UVLF Threshold Mon3
0x43 0x8C 3.6V OVLF Threshold Mon3

0x44

0xAA

102.4µs De-bounce
0x45 0x1C O VHF → NRST, UVHF → NRST, 1kHz LF Cutoff

0X9E

0x01

ESM Threshold = 2ms

0X9F

0x59

Reset Delay 1ms, WD EN

0xA1

0x06

AMSK ON MON2,3

0xA2

0x06

AMSK OFF MON2,3

0xA5,6

0x00

SEQ Timeout = 1ms
0xA8 0x06 SEQ UP Mon2,3 UVLF
0xA9 0x06 SEQ DOWN Mon2,3 UVLF

0xAA

0x27

WD Violation Count = 2, WD Delay = 7

0xAB

0x1D

WD Close = 30ms

0xAC

0x1D

WD Open = 30ms

0xFA

0x00

3.3V I2C interface
Table 10-3 TPS389C03A26RTERQ1 OTP Configuration

ADDR

DATA

Configuration Description

0x00

0x00

DEVICE_MODEL[7:3] and VENDOR_ID[2:0]

0x01

0x42

SILICON_REV[7:6] and OTP_REV[5:0]

0x02

0xF1

Channels disabled. MON2, 3, 4 enabled.

0x11

0x0F

Timestamp & sequence overwrite, PEC enabled.
0x12 0x03 BIST at POR

0x13

0x0E

Enable UVHF interrupt MON 2, 3, 4.
0x14 0x00 UVLF interrupt disabled.

0x15

0x0E

Enable OVHF interrupt MON 2, 3, 4.
0x16 0x00 OVLF interrupt disabled.

0x1B

0x14

Thermal Shut Down Interrupt Enable
0x1C 0x03 BIST complete and fail interrupt enabled.

0x1D

0xAB

NRST MISMATCH, ESM → NIRQ, ESM, WDT → NRST, ESM → WDO not mapped.

0x1E

0x0E

Enable MON 2, 3, 4.

0x1F

0x06

MON 2, 3 x4 Scaling

0x30

0x6E

3.0V UVHF Threshold MON 2

0x31

0x8C

3.6V OVHF Threshold MON 2
0x32 0x76 3.16V UVLF Threshold MON 2
0x33 0x84 3.44V OVLF Threshold MON 2

0x34

0xAA

102.4µs De-Bounce
0x35 0x1C OVHF, UVHF → NRST, 1kHz LF Cutoff

0x40

0x2D

1.7V UVHF Threshold MON 3

0x41

0x37

1.9V OVHF Threshold MON 3
0x42 0x2E 1.72V UVLF Threshold MON 3
0x43 0x36 1.88V OVLF Threshold MON 3

0x44

0xAA

102.4µs De-bounce
0x45 0x1C OVHF, UVHF → NRST, 1kHz LF Cutoff

0x50

0xB4

1.1V UVHF Threshold MON 4

0x51

0xDE

1.31V OVHF Threshold MON 4
0x52 0xBD 1.145V UVLF Threshold MON 4
0x53 0xD2 1.25V OVLF Threshold MON 4

0x54

0xAA

102.4µs De-bounce
0x55 0x1C OVHF, UVHF → NRST, 1kHz LF Cutoff

0X9E

0xFF

ESM Threshold = 864ms

0X9F

0x5C

Reset Delay 20ms, WD EN

0xA1

0x0E

AMSK ON MON 2, 3, 4

0xA2

0x0E

AMSK OFF MON 2, 3, 4

0xA5,6

0x31

SEQ Timeout = 50ms
0xA8 0x00 SEQ UP Mon 2, 3, 4 OFF Threshold
0xA9 0x00 SEQ DOWN Mon 2, 3, 4 OFF Threshold

0xAA

0x71

WD Violation Count = 7, WD Delay = 1

0xAB

0x40

WD Close = 100ms

0xAC

0x40

WD Open = 100ms

0xFA

0x00

3.3V I2C interface