SNVSCC2H November   2022  – April 2025 TPS389C03-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Maskable Interrupt (AMSK)
      3. 7.3.3  VDD
      4. 7.3.4  MON
      5. 7.3.5  NRST
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Packet Error Checking (PEC)
      9. 7.3.9  Q&A Watchdog
        1. 7.3.9.1 Question and Token Generation
        2. 7.3.9.2 Q&A Watchdog Open and Close Window Delay
        3. 7.3.9.3 Q&A Watchdog Status Register
        4. 7.3.9.4 Q&A Watchdog Timing
        5. 7.3.9.5 Q&A Watchdog State Machine and Test Program
      10. 7.3.10 Error Signal Monitoring (ESM)
        1. 7.3.10.1 ESM Timing
      11. 7.3.11 Register Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389C03-Q1 Power ON
  9. 8 Register Maps
    1. 8.1 Registers Overview
      1. 8.1.1 BANK0 Registers
      2. 8.1.2 BANK1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Supply Guidelines
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Documentation Support
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.11 Register Protection

TPS389C03-Q1 features register protection enabled through registers PROT1 0xF1h and PROT2 0xF2h. Registers PROT1 and PROT2 composition is shown in table Table 7-15

Table 7-15 PROT1 Register Description
Register Bit 7 6 5 4 3 2 1 0
PROT1 (0xF1) R/W RSVD RSVD WRKC RSVD CFG IEN MON SEQ
PROT2 (0xF2) R/W RSVD RSVD WRKC RSVD CFG IEN MON SEQ

To write-protect a register group, the host must set the relevant bit in both registers PROT1 and PROT2. Register groups are split up into categories as shown in Table 7-16. Register groups are only applicable to registers in Bank One. Registers concerning ESM and Watchdog are not protected by any register group as seen in Table 7-16.

Table 7-16 Write-Protect Register Group Summary
Register name PROT group Register name PROT group
VMON_CTL WRKC ESM N/A
VMON_MISC CFG TI_CONTROL N/A
TEST_CFG CFG AMSK_ON IEN
IEN_UVHP IEN AMSK_OFF IEN
IEN_UVLP IEN SEQ_TOUT_MSB SEQ
IEN_OVHP IEN SEQ_TOUT_LSB SEQ
IEN_OVLP IEN SEQ_UP_THLD SEQ
IEN_CONTROL IEN SEQ_DN_THLD SEQ
IEN_TEST IEN WDT_CFG N/A
IEN_VENDOR IEN WDT_CLOSE N/A
VIN_CH_EN CFG WDT_OPEN N/A
VRANGE_MULT CFG WDT_QA_CFG N/A
MON2 settings MON[2] WDT_ANSWER N/A
MON3 settings MON[3] BANK_SEL N/A
MON4 settings MON[4]

If individual monitor protection is desired this can be achieved through the use of register PROT_MON (0xF3) as seen in figure Table 7-17.

Table 7-17 PROT_MON Register Description
Register Bit 7 6 5 4 3 2 1 0
PROT_MON (0xF3) R/W RSVD RSVD RSVD RSVD MON[4] MON[3] MON[2] RSVD

Register PROT_MON selects the monitor channel which is protected once PROT1 AND PROT2 registers are written to protect the MON group. Register PROT_MON is set to a value of 0xFF by default, which applies protection to all monitors when MON protection is set through registers PROT1 and PROT2. If a user wishes to not apply protection to a specific monitor channel then the user must set the bit corresponding to the monitor channel in question to a value of 0 prior to PROT1 and PROT2 being set.

At start up registers PROT1 and PROT2 are set to a defult value of 0x00. Once a bit is set to 1 in PROT1 or PROT2 the bit becomes read-only and cannot be cleared by a write command. To reset PROT1 and PROT2 the user can utilize RESET_PROT, bit 3 of the VMON_CTL register. RESET_PROT is part of the WRKC register set therefore if the user desires to use RESET_PROT’s functionality WRKC protection must not be included when configuring PROT1 and PROT2 protection registers. If WRKC protection is enabled when configuring PROT1 and PROT2 then protection registers can only be reset through a device power cycle.