SNVSCF2A November   2025  – May 2026 LM65680

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Wettable Flanks
    2. 5.2 Pinout Design for Clearance and FMEA
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  High-Voltage Bias Supply Subregulator (VCC, BIAS)
      3. 7.3.3  Precision Enable and Adjustable Input Voltage UVLO (EN/UVLO)
      4. 7.3.4  Output Voltage Setpoint (FB, BIAS)
      5. 7.3.5  Switching Frequency (RT)
      6. 7.3.6  Mode Selection and Clock Synchronization (MODE/SYNC)
        1. 7.3.6.1 Clock Synchronization
        2. 7.3.6.2 Clock Locking
      7. 7.3.7  Device Configuration (CNFG/SYNCOUT)
      8. 7.3.8  Dual-Random Spread Spectrum (DRSS)
      9. 7.3.9  High-Side MOSFET Gate Drive (BST)
      10. 7.3.10 Configurable Soft Start (SS)
        1. 7.3.10.1 Recovery From Dropout
      11. 7.3.11 Protection Features
        1. 7.3.11.1 Power-Good Monitor (PG)
        2. 7.3.11.2 Overcurrent and Short-Circuit Protection
        3. 7.3.11.3 Hiccup-Mode Protection
        4. 7.3.11.4 Thermal Shutdown
      12. 7.3.12 Two-Phase, Single-Output Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Train Components
        1. 8.1.1.1 Buck Inductor
        2. 8.1.1.2 Output Capacitors
        3. 8.1.1.3 Input Capacitors
        4. 8.1.1.4 EMI Filter
      2. 8.1.2 Error Amplifier and Compensation
      3. 8.1.3 Maximum Ambient Temperature
        1. 8.1.3.1 Derating Curves
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – 5V, 8A Synchronous Buck Regulator With Wide Input Voltage Range and High Efficiency
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Choosing the Switching Frequency
          3. 8.2.1.2.3  Buck Inductor Selection
          4. 8.2.1.2.4  Input Capacitor Selection
          5. 8.2.1.2.5  Output Capacitors
          6. 8.2.1.2.6  Output Voltage Setpoint
          7. 8.2.1.2.7  Compensation Components
          8. 8.2.1.2.8  Setting the Input Voltage UVLO
          9. 8.2.1.2.9  EMI Mitigation, RDRSS
          10. 8.2.1.2.10 Bootstrap Capacitor, CBST
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2 – High Efficiency, 48V to 12V, 8A, 400kHz Synchronous Buck Regulator
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Buck Inductor Selection
          2. 8.2.2.2.2 Input Capacitor Selection
          3. 8.2.2.2.3 Output Capacitors
          4. 8.2.2.2.4 Output Voltage Setpoint
          5. 8.2.2.2.5 Compensation Components
          6. 8.2.2.2.6 Feedforward Capacitor
          7. 8.2.2.2.7 Soft-Start Capacitor
        3. 8.2.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Thermal Design and Layout
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
        1. 9.2.1.1 Low-EMI Design Resources
        2. 9.2.1.2 Thermal Design Resources
        3. 9.2.1.3 Multiphase Design Resources
        4. 9.2.1.4 PCB Layout Resources
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

Typical values are at TJ = 25°C. Minimum and maximum limits apply at TJ = –40°C to 150°C, unless otherwise stated.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY (VIN)
VINUVLO(R) VIN UVLO rising threshold voltage VIN rising (needed to start up) 3.25 3.4 3.5 V
VINUVLO(F) VIN UVLO falling threshold voltage VIN falling (once operating) 2.5 2.55 V
VINUVLO(H) VIN UVLO hysteresis voltage 0.9 V
IVIN VIN sleep quiescent current, internal COMP, no switching  VIN = 48V, VBIAS = 5V + 2%, CNFG tied to VCC, TJ = 25℃ 0.9 1.4 µA
IBIAS(FIX-3.3V) BIAS quiescent current, fixed 3.3V output, internal COMP, no switching VBIAS = 3.3V + 2%, CNFG tied to VCC, AUTO mode, TJ = 25°C 8 10 µA
IQ(FIX-3.3V) VIN sleep quiescent current, fixed 3.3V output, internal COMP, no switching VIN = 24V, VBIAS = 3.3V + 2%, CNFG tied to VCC, TJ = 25°C, AUTO mode 2.1 2.7 µA
TJ = 125°C  2.1 6.4 µA
IBIAS(FIX-5V) BIAS quiescent current, fixed 5V output, internal COMP, no switching VBIAS = 5V + 2%, CNFG tied to VCC, AUTO mode, TJ = 25°C 9 12 µA
IQ(FIX-5V) VIN total sleep quiescent current, fixed 5V output, internal COMP, no switching VIN = 48V, VBIAS = 5V + 2%, CNFG tied to VCC, TJ = 25°C, AUTO mode 1.8 2.4 µA
TJ = 125°C 1.8 5.8 µA
IBIAS(ADJ-3.3V) BIAS quiescent current, adjustable 3.3V output, internal COMP, no switching VFB = 0.8V + 2%, CNFG tied to VCC, AUTO mode, TJ = 25°C 6.8 8.1 µA
IQ(ADJ-3.3V) VIN total sleep quiescent current, adjustable 3.3V output, internal COMP, no switching VIN = 24V, VFB = 0.8V + 2%, CNFG tied to VCC, AUTO mode, TJ = 25°C 1.9 2.5 µA
IBIAS(ADJ-3.3V-EXT) BIAS quiescent current, adjustable 3.3V output, external COMP, no switching VFB = 0.8V + 2%, RCNFG = 49.9kΩ, AUTO mode, TJ = 25°C  37 44 µA
IQ(ADJ-3.3V-EXT) VIN total sleep quiescent current, adjustable 3.3V output, external COMP, no switching VIN = 24V, VFB = 0.8V + 2%, RCNFG = 49.9kΩ, AUTO mode, TJ = 25°C 6 7.4 µA
IQ-SHD VIN shutdown quiescent current VIN = 48V, VEN/UVLO = 0V, TJ = 25°C 0.8 1.2 µA
VIN = 48V, VEN/UVLO = 0V, TJ = 125°C 0.8 1.8 µA
PRECISION ENABLE (EN/UVLO)
VEN-TH(R) EN/UVLO rising threshold VEN/UVLO rising 1.15 1.25 1.35 V
VEN-TH(F) EN/UVLO falling threshold  VEN/UVLO falling 0.9 1 1.1 V
VEN-HYS EN/UVLO hysteresis  0.25 V
VEN-HYS% Ratio of EN/UVLO hysteresis to rising threshold VEN-HYS/VEN-TH(R) 18 20 22 %
IEN-LKG Enable input leakage current EN/UVLO tied to VIN 0.16 3.5 µA
INTERNAL LDO (VCC)
VVCC1 VCC regulation voltage 3.4V ≤ VIN ≤ 65V, VBIAS = 0V 3.3 V
VVCC2 3.4V ≤ VBIAS ≤ 30V 3.2 V
VBIAS(ON) BIAS switchover rising threshold (VIN to BIAS) VBIAS rising 3.175 3.25 V
VBIAS(OFF) BIAS switchover falling threshold (BIAS to VIN) VBIAS falling 3 3.05 V
VVCC-UVLO(R) VCC UVLO rising threshold IVCC = 0A  3.27 3.4 3.5 V
VVCC-UVLO(F) VCC UVLO falling threshold IVCC = 0A  2.5 V
REFERENCE VOLTAGE (FB)
VFB1 Feedback reference voltage, external COMP FPWM mode, RCNFG = 49.9kΩ 0.792 0.8 0.808 V
VFB2 Feedback reference voltage, internal COMP FPWM mode, CNFG tied to VCC 0.792 0.8 0.808 V
IFB-LKG Feedback pin input leakage current VFB = 0.8V, adjustable VOUT setting 1.8 90 nA
FIXED OUTPUT VOLTAGE (BIAS)
VOUT-3.3V-INT 3.3V fixed output voltage, internal COMP FB tied to GND, CNFG tied to VCC 3.267 3.3 3.337 V
VOUT-3.3V-EXT 3.3V fixed output voltage, external COMP FB tied to GND, RCNFG = 49.9kΩ 3.267 3.3 3.337 V
VOUT-5V-INT 5V fixed output voltage, internal COMP FB tied to VCC, CNFG tied to VCC 4.94 5 5.06 V
VOUT-5V-EXT 5V fixed output voltage, external COMP FB tied to VCC, RCNFG = 49.9kΩ 4.94 5 5.06 V
SOFT START (SS)
tEN-SW Enable HIGH to start of switching delay VFB = VRT = VMODE = GND, VBIAS = VOUT 1.9 2.5 3.1 ms
tSS Internal fixed soft-start time Time from first SW pulse to VFB at 90% of setpoint 2.9 5.3 8.1 ms
ISS SS charge current VSS = 0V 20 µA
RSS SS discharge resistance VEN/UVLO = 0V 7 Ω
ERROR AMPLIFIER (COMP)
gm EA transconductance VCOMP = 0.8V, VFB = 0.8V ±5% 1 mS
VCOMP-EXT(h-clamp) External COMP – high clamp voltage VFB = 0V, adjustable VOUT setting 1.056 V
POWER STAGE (SW)
RDS(on)HS High-side FET on-state resistance ISW = 500mA, VBST – VSW = 3.3V 42 mΩ
RDS(on)LS Low-side FET on-state resistance 23 mΩ
tON(min) Minimum on-time(1)  IOUT = 2A, RRT = 6.81kΩ 36 48 ns
tOFF(min) Minimum off-time VIN = 4V, FSW = 2.2MHz 82 118 ns
tON(max) Maximum on-time FSW = 300kHz 13.3 µs
CURRENT LIMITS AND HICCUP MODE
IHS-LIM1 High-side peak current limit, 8A option Duty cycle approaches 0% 10.7 12.5 13.7 A
ILS-LIM1 Low-side valley current limit, 8A option 8.5 9.9 10.9 A
IL-PK1(AUTO-minD) AUTO-mode peak inductor current at minimum duty cycle, 8A option tON ≤ 100ns 1.9 3 4.1 A
IL-PK1(AUTO-maxD) AUTO-mode peak inductor current at maximum duty cycle, 8A option tON ≥ 1µs 1.1 A
IHS-LIM2 High-side peak current limit, 6A option Duty cycle approaches 0% 8.2 9.5 10.6 A
ILS-LIM2 Low-side valley current limit, 6A option 6.6 7.4 8.2 A
IL-PK2(AUTO-minD) AUTO-mode peak inductor current at minimum duty cycle, 6A option tON ≤ 100ns 1.1 1.9 2.8 A
IL-PK2(AUTO-maxD) AUTO-mode peak inductor current at maximum duty cycle, 6A option tON ≥ 1µs 0.95 A
IHS-LIM3 High-side peak current limit, 4A option Duty cycle approaches 0% 5.9 7 8 A
ILS-LIM3 Low-side valley current limit, 4A option 4.2 5.4 6.3 A
IL-PK3(AUTO-minD) AUTO-mode peak inductor current at minimum duty cycle, 4A option tON ≤ 100ns 1 1.8 2.7 A
IL-PK3(AUTO-maxD) AUTO-mode peak inductor current at maximum duty cycle, 4A option tON ≥ 1µs 0.65 A
ILS-NEG-LIM Low-side negative current limit Sinking current limit, FPWM mode –9.6 –6.9 –4.9 A
IL-ZC Zero-cross threshold AUTO mode 100 mA
VHIC FB voltage hiccup threshold Low-side FET on-time > 165ns, after soft start 0.32 V
tHICDLY Hiccup mode activation delay 64 cycles
tHIC Hiccup mode duration time Internal soft start 48 ms
POWER GOOD (PG)
VPG-OV(R) PG OV rising threshold % of FB voltage (ADJ output) or BIAS voltage (fixed output) 103 105 107 %
VPG-OV(F) PG OV falling threshold 101 104 106 %
VPG-UV(R) PG UV rising threshold 94 96 98.5 %
VPG-UV(F) PG UV falling threshold 92.5 95 97 %
tPG-DEGLITCH(R) Deglitch filter delay on PG rising edge 1.2 2 3 ms
tPG-DEGLITCH(F) Deglitch filter delay on PG falling edge 55 130 175 µs
VIN(PG-VALID) Minimum VIN for valid PG output VPG(OL) < 0.4V, RPG =  49.9kΩ, VPG = 5V 1.25 V
VPG(OL) PG low-state voltage IPG = 1mA, VIN = 1.25V 0.4 V
RPG(on) PG switch on resistance IPG = 1mA 51 110 Ω
SWITCHING FREQUENCY (RT)
fSW1 Switching frequency RT tied to PGND 1.98 2.2 2.42 MHz
RRT = 6.81kΩ ±1% 1.98 2.2 2.42 MHz
fSW2 RRT = 15.8kΩ ±1% 900 1000 1100 kHz
fSW3 RRT = 40.2kΩ ±1% 360 400 440 kHz
RT tied to VCC 360 400 440 kHz
SYNCHRONIZATION (MODE/SYNC)
VSYNC(IL) SYNC input low-level threshold 0.45 V
VSYNC(IH) SYNC input high-level threshold 1.3 V
VSYNCOUT(OL) SYNCOUT output low-level threshold ISYNCOUT = 2mA 0.4 V
VSYNCOUT(OH) SYNCOUT output high-level threshold ISYNCOUT = –2mA 2.4 V
fSYNC-RANGE1 Synchronization frequency range for set 2.2MHz RRT = 6.81kΩ ±1% 1.76 2.64 MHz
fSYNC-RANGE2 Synchronization frequency range for set 300kHz RRT = 54.2kΩ ±1% 240 360 kHz
tSYNC-LOW(min) Minimum low pulse width of external SYNC signal 80 ns
tSYNC-HIGH(min) Minimum high pulse width of external SYNC signal 80 ns
tSYNC-SW-DLY SYNC to SW delay time(1) –22 22 ns
tMODE-DLY MODE change delay time(1) 20 µs
DUAL RANDOM SPREAD SPECTRUM (DRSS/MCOMM)
ΔfSS-LF Low-frequency triangular spread spectrum modulation range DRSS/MCOMM open 17 %
fm-LF Triangular modulation frequency DRSS/MCOMM open 3.6 6 8.4 kHz
ΔfSS-HF High-frequency pseudo-random spread spectrum modulation range DRSS/MCOMM open 2 %
THERMAL SHUTDOWN
TSHD Thermal shutdown(1) Shutdown threshold 155 165 177 ºC
Recovery threshold 156 ºC
(1) Specified by design.