SNVSCQ2A March   2025  – August 2025 LP5817

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Dimming
      2. 7.3.2 PWM Dimming
      3. 7.3.3 Sloper
      4. 7.3.4 Protections
        1. 7.3.4.1 UVLO
        2. 7.3.4.2 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Initialization Mode
      2. 7.4.2 Standby and Normal Mode
      3. 7.4.3 Shutdown Mode
      4. 7.4.4 Thermal Shutdown Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Data Tansactions
      2. 7.5.2 I2C Data Format
      3. 7.5.3 Command Description
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Parameters
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Program Procedure
        2. 8.2.3.2 Programming Example
      4. 8.2.4 Application Performance Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.6 Timing Requirements

Unless specified otherwise, typical characteristics apply over the full ambient temperature range (–40°C < TA < +85°C ), VCC = 3.6V, CIN = 1μF.
I2C Timing Requirements MIN NOM MAX UNIT
Standard-mode
fSCL SCL clock frequency 0 100 kHz
1 Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 µs
2 LOW period of the SCL clock 4.7 µs
3 HIGH period of the SCL clock 4 µs
4 Set-up time for a repeated START condition 4.7 µs
5 Data hold time 0 µs
6 Data set-up time 250 ns
7 Rise time of both SDA and SCL signals 1000 ns
8 Fall time of both SDA and SCL signals 300 ns
9 Set-up time for STOP condition 4 µs
10 Bus free time between a STOP and START condition 4.7 µs
Cb Capacitive load for each bus line 400 pF
Fast-mode
fSCL SCL clock frequency 0 400 kHz
1 Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.6 µs
2 LOW period of the SCL clock 1.3 µs
3 HIGH period of the SCL clock 0.6 µs
4 Set-up time for a repeated START condition 0.6 µs
5 Data hold time 0 µs
6 Data set-up time 100 ns
7 Rise time of both SDA and SCL signals 300 ns
8 Fall time of both SDA and SCL signals 300 ns
9 Set-up time for STOP condition 0.6 µs
10 Bus free time between a STOP and START condition 1.3 µs
Cb Capacitive load for each bus line 400 pF