SNVSCS3 February   2025 LP5892-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Independent and Stackable Mode
        1. 6.3.1.1 Independent Mode
        2. 6.3.1.2 Stackable Mode
      2. 6.3.2 Current Setting
        1. 6.3.2.1 Brightness Control (BC) Function
        2. 6.3.2.2 Color Brightness Control (CC) Function
        3. 6.3.2.3 Choosing BC/CC for a Different Application
      3. 6.3.3 Frequency Multiplier
      4. 6.3.4 Line Transitioning Sequence
      5. 6.3.5 Protections and Diagnostics
        1. 6.3.5.1 Thermal Shutdown Protection
        2. 6.3.5.2 IREF Resistor Short Protection
        3. 6.3.5.3 LED Open Load Detection and Removal
          1. 6.3.5.3.1 LED Open Detection
          2. 6.3.5.3.2 Read LED Open Information
          3. 6.3.5.3.3 LED Open Caterpillar Removal
        4. 6.3.5.4 LED Short and Weak Short Circuitry Detection and Removal
          1. 6.3.5.4.1 LED Short/Weak Short Detection
          2. 6.3.5.4.2 Read LED Short Information
          3. 6.3.5.4.3 LSD Caterpillar Removal
    4. 6.4 Device Functional Modes
    5. 6.5 Continuous Clock Series Interface
      1. 6.5.1 Data Validity
      2. 6.5.2 CCSI Frame Format
      3. 6.5.3 Write Command
        1. 6.5.3.1 Chip Index Write Command
        2. 6.5.3.2 VSYNC Write Command
        3. 6.5.3.3 MPSM Write Command
        4. 6.5.3.4 Standby Clear and Enable Command
        5. 6.5.3.5 Soft_Reset Command
        6. 6.5.3.6 Data Write Command
      4. 6.5.4 Read Command
    6. 6.6 PWM Grayscale Control
      1. 6.6.1 Grayscale Data Storage and Display
        1. 6.6.1.1 Memory Structure Overview
        2. 6.6.1.2 Details of Memory Bank
        3. 6.6.1.3 Write a Frame Data into Memory Bank
      2. 6.6.2 PWM Control for Display
    7. 6.7 Register Maps
      1. 6.7.1  FC0
      2. 6.7.2  FC1
      3. 6.7.3  FC2
      4. 6.7.4  FC3
      5. 6.7.5  FC4
      6. 6.7.6  FC14
      7. 6.7.7  FC15
      8. 6.7.8  FC17
      9. 6.7.9  FC19
      10. 6.7.10 FC20
      11. 6.7.11 FC21
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 System Structure
        2. 7.2.1.2 SCLK Frequency
        3. 7.2.1.3 Internal GCLK Frequency
        4. 7.2.1.4 Line Switch Time
        5. 7.2.1.5 Blank Time Removal
        6. 7.2.1.6 BC and CC
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Chip Index Command
        2. 7.2.2.2 FC Registers Settings
        3. 7.2.2.3 Grayscale Data Write
        4. 7.2.2.4 VSYNC Command
        5. 7.2.2.5 LED Open, Short Read
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.4 Line Transitioning Sequence

The LP5892-Q1 defines a timing sequence of scan line transition, shown as Figure 6-4. T_SW is the total transitioning time. T_SW is broken up into four intervals: T0 is the time interval between the end of PWM time in current segment and the beginning of channel pre-discharge, T1 is the time interval between the beginning of the channel pre-discharge and the beginning of current line OFF, T2 is the time interval that the beginning of current line OFF and the beginning of next line ON, T3 is the time interval of the beginning of next line ON and the beginning of PWM time in next segment.

LP5892-Q1 Line Transitioning Sequence Figure 6-4 Line Transitioning Sequence

The line switch time T_SW equals to T0 + T1 + T2 + T3. T_SW can be configured by the LINE_SWT (see FC1 register bit 40-37 in Table 6-8).

Table 6-4 is the relation between LINE_SWT bits and the line switch time (GCLK numbers) with different internal GCLK frequency.

Table 6-4 Line Switch Time
LINE_SWT GCLK Numbers T_SW (us, 40 MHZ GCLK) T_SW (us, 60 MHZ GCLK) T_SW (us, 100 MHZ GCLK) T_SW (us, 120 MHZ GCLK) T_SW (us, 160 MHZ GCLK)
0000b 45 1.125 0.7515 0.45 0.3735 0.2835
0001b 60 1.5 1.002 0.6 0.498 0.378
0010b 90 2.25 1.503 0.9 0.747 0.567
0011b 120 3 2.004 1.2 0.996 0.756
0100b 150 3.75 2.505 1.5 1.245 0.945
0101b 180 4.5 3.006 1.8 1.494 1.134
0110b 210 5.25 3.507 2.1 1.743 1.323
0111b 240 6 4.008 2.4 1.992 1.512
1000b 270 6.75 4.509 2.7 2.241 1.701
1001b 300 7.5 5.01 3 2.49 1.89
1010b 330 8.25 5.511 3.3 2.739 2.079
1011b 360 9 6.012 3.6 2.988 2.268
1100b 390 9.75 6.513 3.9 3.237 2.457
1101b 420 10.5 7.014 4.2 3.486 2.646
1110b 450 11.25 7.515 4.5 3.735 2.835
1111b 480 12 8.016 4.8 3.984 3.024