SNVSCS3 February   2025 LP5892-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Independent and Stackable Mode
        1. 6.3.1.1 Independent Mode
        2. 6.3.1.2 Stackable Mode
      2. 6.3.2 Current Setting
        1. 6.3.2.1 Brightness Control (BC) Function
        2. 6.3.2.2 Color Brightness Control (CC) Function
        3. 6.3.2.3 Choosing BC/CC for a Different Application
      3. 6.3.3 Frequency Multiplier
      4. 6.3.4 Line Transitioning Sequence
      5. 6.3.5 Protections and Diagnostics
        1. 6.3.5.1 Thermal Shutdown Protection
        2. 6.3.5.2 IREF Resistor Short Protection
        3. 6.3.5.3 LED Open Load Detection and Removal
          1. 6.3.5.3.1 LED Open Detection
          2. 6.3.5.3.2 Read LED Open Information
          3. 6.3.5.3.3 LED Open Caterpillar Removal
        4. 6.3.5.4 LED Short and Weak Short Circuitry Detection and Removal
          1. 6.3.5.4.1 LED Short/Weak Short Detection
          2. 6.3.5.4.2 Read LED Short Information
          3. 6.3.5.4.3 LSD Caterpillar Removal
    4. 6.4 Device Functional Modes
    5. 6.5 Continuous Clock Series Interface
      1. 6.5.1 Data Validity
      2. 6.5.2 CCSI Frame Format
      3. 6.5.3 Write Command
        1. 6.5.3.1 Chip Index Write Command
        2. 6.5.3.2 VSYNC Write Command
        3. 6.5.3.3 MPSM Write Command
        4. 6.5.3.4 Standby Clear and Enable Command
        5. 6.5.3.5 Soft_Reset Command
        6. 6.5.3.6 Data Write Command
      4. 6.5.4 Read Command
    6. 6.6 PWM Grayscale Control
      1. 6.6.1 Grayscale Data Storage and Display
        1. 6.6.1.1 Memory Structure Overview
        2. 6.6.1.2 Details of Memory Bank
        3. 6.6.1.3 Write a Frame Data into Memory Bank
      2. 6.6.2 PWM Control for Display
    7. 6.7 Register Maps
      1. 6.7.1  FC0
      2. 6.7.2  FC1
      3. 6.7.3  FC2
      4. 6.7.4  FC3
      5. 6.7.5  FC4
      6. 6.7.6  FC14
      7. 6.7.7  FC15
      8. 6.7.8  FC17
      9. 6.7.9  FC19
      10. 6.7.10 FC20
      11. 6.7.11 FC21
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 System Structure
        2. 7.2.1.2 SCLK Frequency
        3. 7.2.1.3 Internal GCLK Frequency
        4. 7.2.1.4 Line Switch Time
        5. 7.2.1.5 Blank Time Removal
        6. 7.2.1.6 BC and CC
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Chip Index Command
        2. 7.2.2.2 FC Registers Settings
        3. 7.2.2.3 Grayscale Data Write
        4. 7.2.2.4 VSYNC Command
        5. 7.2.2.5 LED Open, Short Read
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.5.1 Data Validity

The data on DIN wire must be stable at rising edges of the SCLK in transmission.