SNVSCW9 April 2025 TPS371K-Q1
ADVANCE INFORMATION
5 Pin Configuration and Functions
Figure 5-1 DFX Package,15-Pin SOIC,
TPS371KA-Q1 Adjustable Version (Top View)
Figure 5-3 DFX Package,15-Pin SOIC,
TPS371K-Q1 Fixed Version (Top View)
Figure 5-2 DFX Package,15-Pin SOIC,
TPS371KB-Q1 Adjustable Version (Top View)
| OPN Pinout | Pin 8**** | Pin 10 *** | Pin 13 ** | Pin 14 * |
|---|---|---|---|---|
| A | BIST EN | BIST | OUT UV | OUT OV |
| B | NC | NC | OUT UV | OUT OV |
| C | BIST EN | LOW UV & BIST | OUT UV | OUT OV |
| D | NC | LOW UV | OUT UV | OUT OV |
| E | BIST EN | BIST | LOW UV | OUT OV |
| F | NC | NC | LOW UV | OUT OV |
| PIN | I/O | DESCRIPTION | |||
|---|---|---|---|---|---|
| NAME | TPS371KANO. | TPS371KBNO. | TPS371K Fixed NO. | ||
| SENSE | 1 | 1 | 1 | I | Sense Voltage: Connect this pin to the voltage rail that must be monitored. |
| GND | 4, 7 | 4, 7 | 4,5,6,9 | - | Ground. All GND pins must be electrically connected to the board ground. |
| CTR | 5 | 5 | 10 | O | Release Time Delay: User-programmable release time delay for output pins. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. See Device Nomenclature table for output pin configurations. |
| CTS | 6 | 6 | 11 | O | SENSE Time Delay: User-programmable sense time delay for SENSE. Connect an external capacitor for adjustable time delay or leave the pin floating for the shortest delay. See Device Nomenclature table for output pin configurations. |
| VSENSE | 9 | - | - | O | Voltage SENSE: The output of the integrated buffer that is a scaled down voltage of the SENSE pin. See Device Nomenclature table for output pin configurations. |
| ADJ UV | 11 | 11 | - | I | Adjustable Undervoltage Threshold: User can program the internal undervoltage thresholds by using external resistors to set a voltage at start-up. See voltage threshold table for selectable threshold options. |
| ADJ OV | 12 | 12 | - | I | Adjustable Overvoltage Threshold: User can program the internal overvoltage threshold by using external resistors to set a voltage at start-up. See voltage threshold table for selectable threshold options. |
| OUT UV | See Pinout Table | See Pinout Table | 7 | O | Output Undervoltage Signal: OUT UV asserts when SENSE crosses the undervoltage threshold. Assertion time delay is either fixed or set by CTS. OUT UV remains asserted for the release time delay period after SENSE transitions out of a fault condition. The active low open-drain release output requires an external pullup resistor. See Device Nomenclature table for OUT UV threshold and timing configurations. Output topology: Open-Drain Active-Low |
| OUT OV | See Pinout Table | See Pinout Table | 14 | O | Output Overvoltage Signal: OUT OV asserts when SENSE crosses the Overvoltage threshold. Assertion time delay is either fixed or set by CTS. OUT OV remains asserted for the release time delay period after SENSE transitions out of a fault condition. The active low open-drain release output requires an external pullup resistor. See Device Nomenclature table for OUT OV threshold and timing configurations. Output topology: Open-Drain Active-Low |
| LOW UV | See Pinout Table | See Pinout Table | - | O | Output Low Undervoltage Signal: OUT Low UV asserts when SENSE crosses the Low Overvoltage threshold after the sense time delay, set by CTS. OUT Low UV remains asserted for the release time delay period after SENSE transitions out of a fault condition. The active low open-drain release output requires an external pullup resistor. Output topology: Open-Drain Active-Low |
| BIST | See Pinout Table | See Pinout Table | - | O | Output Built-in
Self-test (BIST): BIST asserts when BIST is in operation.
BIST operation is initiated at device start-up and by a rising edge
on BIST_EN pin. BIST is a device diagnostic test that checks for
internal failures. If there is a failure, BIST stays asserted. Upon
successful BIST, BIST pin de-asserts. Output topology: Open-Drain Active-Low |
| BIST_EN | See Pinout Table | See Pinout Table | - | I | Built-in Self-test Enable (BIST EN): A rising edge on BIST enable pin initiates the BIST. For variants with latch, BIST EN also enables and disables latch. |
| VDD | 15 | 15 | 15 | I | Input Supply Voltage: Supply voltage pin. Bypass with a 0.1µF capacitor to GND for noisy environments. |
| NC | 2, 3, 8 | 2, 3, 8 | 2, 4, 8, 12 | - | No Connect: Leave pins floating or connect to GND. |
| DNC | - | 7 | 13 | - | Do Not Connect: Leave pins floating for proper operation. |