The LP8752x-Q1 device contains a CLKIN input to synchronize switching clock of the buck regulator with the external clock. Depending on the PLL_MODE[1:0] bits (in PLL_CTRL register) and the external clock availability, the external clock is selected and interrupt is generated. Optionally, mask this interrupt with the SYNC_CLK_MASK bit in TOP_MASK1 register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits (in PLL_CTRL register) and ranges from 1MHz to 24MHz with 1MHz steps. The external clock must be inside accuracy limits (–30%/+10%) for valid clock detection. For more information on this function, see the device-specific data sheet.