SNVU755A January   2021  – June 2021 TLV841

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Related Documentation
    2. 1.2 TLV841 Applications
  3. 2Schematic, Bill of Materials, and Layout
    1. 2.1 TLV841EVM Schematic
    2. 2.2 TLV841EVM Bill of Materials
    3. 2.3 Layout and Component Placement
    4. 2.4 Layout
  4. 3EVM Connectors
    1. 3.1 EVM Test Points
    2. 3.2 EVM Jumpers
  5. 4EVM Setup and Operation
    1. 4.1 Input Power (VDD)
    2. 4.2 Monitoring Voltage on SENSE Pin (TLV841S)
    3. 4.3 Monitoring Voltage on VDD (TLV841M and TLV841C)
    4. 4.4 Manual Reset (MR) (TLV841M)
    5. 4.5 Reset Output (RESET)
    6. 4.6 Reset Time Delay Programming (Program tD via CT) (TLV841C)
  6. 5Revision History

Manual Reset (MR) (TLV841M)

The TLV841M device variant option offers a Manual Reset (MR) pin that is utilized via jumper J8 (short pin 1 [MR] to pin 2 [GND]). If a shunt jumper is placed on jumper J8, the RESET pin is asserted and forced into a low state. After the shunt jumper is removed and VDD is above its reset threshold, MR returns to a logic high due to the internal pull-up resistor, and RESET is de-asserted to a logic high after the user-defined delay expires. If jumper J8 is left floating, the device operates normally as the MR pin defaults to a logic high via internal pull-up resistor. Pin 1 of jumper J8 can also be connected to a control signal to set the logic level on MR pin. If pin 1 on jumper J8 is a logic low, the device asserts a reset. There is also test point TP3 connected directly to the MR pin in case the user wants to monitor the MR pin.