SPMU381 User guide

SPMU381A April 2026 – August 2026 TPS25752A

6.1 TPS25752A Registers

Table 6-1 lists the memory-mapped registers for the TPS25752A registers. All register offset addresses not listed in Table 6-1 should be considered as reserved locations and the register contents should not be modified.

Table 6-1 TPS25752A Registers

Offset	Acronym	Register Name	Section
3h	Mode	Mode	Section 6.1.1
6h	Customer Use	Customer Use	Section 6.1.2
8h	Command Register (CMD1) for I2Ct	Command Register (CMD1) for I2Ct	Section 6.1.3
9h	Data Register (DATA1) for CMD1	Data Register (DATA1) for CMD1	Section 6.1.4
Fh	Version	Version	Section 6.1.5
14h	Interrupt Event for I2Ct_IRQ	Interrupt Event for I2Ct_IRQ	Section 6.1.6
16h	Interrupt Mask for I2Ct_IRQ	Interrupt Mask for I2Ct_IRQ	Section 6.1.7
18h	Interrupt Clear for I2Ct_IRQ	Interrupt Clear for I2Ct_IRQ	Section 6.1.8
1Ah	Status	Status	Section 6.1.9
26h	Power Path Status	Power Path Status	Section 6.1.10
27h	Global System Configuration	Global System Configuration	Section 6.1.11
28h	Port Configuration	Port Configuration	Section 6.1.12
29h	Port Control	Port Control	Section 6.1.13
2Dh	Boot Flags	Boot Flags	Section 6.1.14
31h	Received Sink Capabilities	Received Sink Capabilities	Section 6.1.15
32h	Transmit Source Capabilities	Transmit Source Capabilities	Section 6.1.16
34h	Active PDO Contract	Active PDO Contract	Section 6.1.17
35h	Active RDO Contract	Active RDO Contract	Section 6.1.18
3Fh	Power Status	Power Status	Section 6.1.19
42h	PD3 Configuration	PD3 Configuration	Section 6.1.20
48h	Received SOP Identity Data Object	Received SOP Identity Data Object	Section 6.1.21
5Ch	IO Config	IO Config	Section 6.1.22
69h	Type C State	Type C State	Section 6.1.23
6Ah	ADC Results	ADC Results	Section 6.1.24
70h	Sleep Control Register	Sleep Control Register	Section 6.1.25
72h	GPIO Status	GPIO Status	Section 6.1.26
73h	TX Manufactrer Info SOP	TX Manufactrer Info SOP	Section 6.1.27
77h	Tx Source Capabilities Extended Data Block	Tx Source Capabilities Extended Data Block	Section 6.1.28
78h	TX Source Info	TX Source Info	Section 6.1.29
7Ah	Transmitted PPS Status Data Block	Transmitted PPS Status Data Block	Section 6.1.30
7Bh	Transmitted Battery Status Data Objects (BSDO) Register	Transmitted Battery Status Data Objects (BSDO) Register	Section 6.1.31
7Dh	Tx Battery Capabilities	Tx Battery Capabilities	Section 6.1.32
98h	Liquid Detection Configuration	Liquid Detection Configuration	Section 6.1.33
A4h	Rx MIDB	Rx MIDB	Section 6.1.34
B2h	Liquid Detection STATUS Register	Liquid Detection STATUS Register	Section 6.1.35

Complex bit access types are encoded to fit into small table cells. Table 6-2 shows the codes that are used for access types in this section.

Table 6-2 TPS25752A Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

6.1.1 Mode Register (Offset = 3h) [Reset = 00000000h]

Mode is shown in Table 6-3.

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Indicates the operational state of the port. The PD Controller has limited functionality in some modes.

Table 6-3 Mode Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h
31-0	Mode	R	0h	The mode described in 4 ASCII characters. 'APP ' indicates that the PD Controller is fully functioning in the application firmware where all registers are available. 'PTCH' indicates that the PD controller is in patch mode. Any value other than 'APP ' indicates that the PD controller is functioning in limited capacity. In 'PTCH' mode, only the following register addresses are accessible: MODE (0x03), Command (0x08), Data (0x09), INT_EVENT (0x14), INT_MASK (0x16), INT_CLEAR (0x18), and BOOT_FLAGS (0x2D).

6.1.2 Customer Use Register (Offset = 6h) [Reset = 0000000000000000h]

Customer Use is shown in Table 6-4.

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This register is allocated for customer use. It is typically used for version control, but usage flexibility remains with the customer.

Table 6-4 Customer Use Register Field Descriptions

Bit	Field	Type	Reset	Description
63-0	Customer Use	R	0h	These 8 bytes are allocated for customer use as needed. The PD Controller does not use this register. This register can only be changed during application customization, not at runtime.

6.1.3 Command Register (CMD1) for I2Ct (Offset = 8h) [Reset = 00000000h]

Command Register (CMD1) for I2Ct is shown in Table 6-5.

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Command register. The PD Controller clears it on initialization and after completing a command.

Table 6-5 Command Register (CMD1) for I2Ct Field Descriptions

Bit	Field	Type	Reset	Description
31-0	Command	R/W	0h	Command register for the command interface. The PD Controller clears this register to 0x0 on initialization and after completing any recognized commands. Unrecognized commands are overwritten with !CMD.

6.1.4 Data Register (DATA1) for CMD1 (Offset = 9h) [Reset = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000h]

Data Register (DATA1) for CMD1 is shown in Table 6-6.

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Data register (DATA1) for the command interface (CMD1).

Table 6-6 Data Register (DATA1) for CMD1 Field Descriptions

Bit	Field	Type	Reset	Description
511-0	Data	R/W	0h	Data register (DATA1) for the command interface (CMD1). The first byte of this register will contain the return code if applicable, and the remaining bytes will contain the command's output

6.1.5 Version Register (Offset = Fh) [Reset = 00000000h]

Version is shown in Table 6-7.

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Bootloader/application code version. Represented as VVVV.MM.RR. The version information is returned in little Endian format i.e. byte 1 = RR, byte 2 = MM, etc.

Table 6-7 Version Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	Version	R	0h	Bootloader/application code version. Represented as VVVV.MM.RR. The version information is returned in little Endian format i.e. byte 1 = RR, byte 2 = MM, etc.

6.1.6 Interrupt Event for I2Ct_IRQ Register (Offset = 14h) [Reset = 0000000000000000000000h]

Interrupt Event for I2Ct_IRQ is shown in Table 6-8.

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Interrupt event bit field for IRQ. If any bit in this register is 1, then the IRQ pin is pulled low. Only the interrupt events enabled in INT_MASK1 (0x16) will be asserted.

Table 6-8 Interrupt Event for I2Ct_IRQ Register Field Descriptions

Bit	Field	Type	Reset	Description
87-84	RESERVED	R	0h
83	System Fault Indicator	R	0h	Stores fault from an external device, no additional action taken.
82	I2C Controller NACked	R	0h	A transaction on the I2C Controller was NACKed
81	Ready for Patch	R	0h	The device is ready for a patch bundle from the host
80	Patch Loaded	R	0h	A patch has been loaded to the device
79-67	RESERVED	R	0h
66	MBRD Buffer Ready	R	0h	The memory buffer is full and ready to be read using the 'MBRd' command
65	TX Memory Buffer Empty	R	0h	The transmit memory buffer is empty
64-61	RESERVED	R	0h
60	Liquid Detection	R	0h	The Liquid Detection state has changed.
59-52	RESERVED	R	0h
51	Discover Mode Completed	R	0h	The Discover Modes process has completed
50-44	RESERVED	R	0h
43	Plug Early Notification	R	0h	A connection has been detected but not yet debounced
42	Sink Transition Completed	R	0h	A source power transition has been initiated tSrcTransition ms after sending an Accept message to a Port Partner Request message
41-40	RESERVED	R	0h
39	Message Data Error	R	0h	An erroneous message has been received from the Port Partner
38	Protocol Error	R	0h	An unexpected message has been received from the Port Partner
37	RESERVED	R	0h
36	Missing Get Capabalities Message Error	R	0h	The Port Partner did not respond to a Get_Sink_Cap message
35	Power Event Occurred Error	R	0h	An OVP, ILIM, or TSD event on VBUS has been detected.
34	Can Provide Voltage or Current Later Error	R	0h	A "Wait" message has been sent or received indicating the Source cannot provide acceptable power at the present time
33	Cannot Provide Voltage or Current Error	R	0h	The USB PD Source cannot provide an acceptable voltage and/or current. A Reject message has been sent to the Sink or a Capability Mismatch has been received from the Sink
32	Device Incompatible Error	R	0h	A USB PD device with an incompatible specification version has been connected, or the Port Partner is not USB PD capable
31	RESERVED	R	0h
30	CMD1 Complete	R	0h	Set whenever a non-zero value in CMD1 register is set to zero or !CMD.
29	MIDB Received	R	0h	A Manufacturer Info message has been received
28	RESERVED	R	0h
27	PD Status Updated	R	0h	The contents of the PD_STATUS (0x40) register have changed
26	Status Updated	R	0h	The contents of the STATUS (0x1A) register have changed
25	RESERVED	R	0h
24	Power Status Updated	R	0h	The contents of the POWER_STATUS (0x3F) register have changed
23	Power Path Switch Changed	R	0h	The contents of the POWER_PATH_STATUS (0x26) register have changed
22	RESERVED	R	0h
21	USB Host No Longer Present	R	0h	The UsbHostPresent field in the STATUS register has transitioned to a value other than 11b
20	USB Host Present	R	0h	The UsbHostPresent field in the STATUS register has transitioned to 11b
19-16	RESERVED	R	0h
15	Sink Cap Message Received	R	0h	A Sink Capabilities message has been received from the Port Partner
14	RESERVED	R	0h
13	New Contract as Provider	R	0h	A PD contract has been formed as a Source. This is asserted after the PS_RDY message has been sent. See ACTIVE_CONTRACT_PDO (0x34) register and ACTIVE_CONTRACT_RDO (0x35) register for details
12-10	RESERVED	R	0h
9	Overcurrent	R	0h	An Overcurrent field (VBUS or VCONN) in the POWER_PATH_STATUS (0x26) register has changed
8-6	RESERVED	R	0h
5	Data Swap Complete	R	0h	A Data Role Swap has completed. See STATUS (0x1A) register and PD_STATUS (0x40) register for port state.
4	RESERVED	R	0h
3	Plug Insert or Removal	R	0h	USB Plug Status has changed. See STATUS (0x1A) register for more plug details.
2	RESERVED	R	0h
1	PD Hardreset	R	0h	A PD Hard Reset has been performed. See PD_STATUS.HardResetDetails for more information.
0	RESERVED	R	0h

6.1.7 Interrupt Mask for I2Ct_IRQ Register (Offset = 16h) [Reset = 0000000000000000000000h]

Interrupt Mask for I2Ct_IRQ is shown in Table 6-9.

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Interrupt mask bit field for INT_EVENT1. Bytes 1 to 10 of this register must be configured through the Application Customization Tool to enable the corresponding interrupt events. For Byte 11, Bit 1 is enabled by default - It is recommended to set the remaining implemented bits as needed by the host application.

Table 6-9 Interrupt Mask for I2Ct_IRQ Register Field Descriptions

Bit	Field	Type	Reset	Description
87-84	RESERVED	R	0h
83	System Fault Indicator	R/W	0h	Set to indicate a fault from an external device in the system.
82	I2C Controller NACKed	R/W	0h	Set to enable notification when a transaction on the I2C Controller is NACKed
81	Ready for Patch	R/W	0h	Set to enable notification when the device is ready for a patch bundle from the host. This bit is set by default by the device.
80	Patch Loaded	R/W	0h	Set to enable notification when a patch is loaded
79-67	RESERVED	R	0h
66	MBRD Buffer Ready	R/W	0h	Set to enable notification when the memory buffer is full and ready to be read using the 'MBRd' command
65	TX Memory Buffer Empty	R/W	0h	Set to enable notification when the transmit memory buffer is empty
64-61	RESERVED	R	0h
60	Liquid Detection	R/W	0h	Set to enable notification when the Liquid Detection state changes
59-52	RESERVED	R	0h
51	Discover mode Completed	R/W	0h	Set to enable notification when the Discover Modes process has completed
50-47	RESERVED	R	0h
46	Unable to Source Error	R/W	0h	Set to enable notification when the Source is unable to increase the voltage to the negotiated contract voltage
45-44	RESERVED	R	0h
43	Plug Early Notification	R/W	0h	Set to enable notification when a connection is detected but not yet debounced
42	Sink Transition Completed	R/W	0h	Set to enable notification when a source power transition is initiated after accepting a Port Partner Request message
41-40	RESERVED	R	0h
39	Message Data Error	R/W	0h	Set to enable notification when an erroneous message is received from the Port Partner
38	Protocol Error	R/W	0h	Set to enable notification when an unexpected message is received from the Port Partner
37	RESERVED	R	0h
36	Missing Get Capabalities Message Error	R/W	0h	Set to enable notification when the Port Partner does not respond to a Get_Sink_Cap or Get_Source_Cap message
35	Power Event Occurred Error	R/W	0h	Set to enable notification when an OVP, ILIM, or TSD event on VBUS is detected
34	Can Provide Voltage or Current Later Error	R/W	0h	Set to enable notification when a "Wait" message is sent or received for Source power availability
33	Cannot Provide Voltage or Current Error	R/W	0h	Set to enable notification when the USB PD Source cannot provide an acceptable voltage and/or current
32	Device Incompatible Error	R/W	0h	Set to enable notification when a USB PD device with an incompatible specification version is connected, or the Port Partner is not USB PD capable
31	RESERVED	R	0h
30	CMD1 Complete	R/W	0h	Set to enable notification when a CMD1 (0x08) register command has completed
29	MIDB Received	R/W	0h	Set to enable notification when a Manufacturer Info message is received
28	RESERVED	R	0h
27	PD Status Updated	R/W	0h	Set to enable notification when the contents of the PD_STATUS (0x40) register change
26	Status Updated	R/W	0h	Set to enable notification when the contents of the STATUS (0x1A) register change
25	RESERVED	R	0h
24	Power Status Updated	R/W	0h	Set to enable notification when the contents of the POWER_STATUS (0x3F) register change
23	Power Path Switch Changed	R/W	0h	Set to enable notification when the contents of the POWER_PATH_STATUS (0x26) register change
22	RESERVED	R	0h
21	USB Host No Longer Present	R/W	0h	Set to enable notification when the UsbHostPresent field in the STATUS register transitions to a value other than 11b
20	USB Host Present	R/W	0h	Set to enable notification when UsbHostPresent field in the STATUS register transitions to 11b
19-16	RESERVED	R	0h
15	Sink Cap Message Received	R/W	0h	Set to enable notification when a Sink Capabilities message is received from the Port Partner
14	RESERVED	R	0h
13	New Contract as Provider	R/W	0h	Set to enable notification when a PD contract is formed as a Source
12-10	RESERVED	R	0h
9	Overcurrent	R/W	0h	Set to enable notification when an Overcurrent field (VBUS or VCONN) in the POWER_PATH_STATUS (0x26) register changes
8-4	RESERVED	R	0h
3	Plug Insert or Removal	R/W	0h	Set to enable notification when USB Plug Status changes
2	RESERVED	R	0h
1	PD Hardreset	R/W	0h	Set to enable notification when a PD Hard Reset is performed
0	RESERVED	R	0h

6.1.8 Interrupt Clear for I2Ct_IRQ Register (Offset = 18h) [Reset = 0000000000000000000000h]

Interrupt Clear for I2Ct_IRQ is shown in Table 6-10.

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Interrupt clear bit field for INT_EVENT1. Writing 1 to a specific bit will clear that specific event in INT_EVENT1. Bits set in this register are cleared from INT_EVENT1.

Table 6-10 Interrupt Clear for I2Ct_IRQ Register Field Descriptions

Bit	Field	Type	Reset	Description
87-83	RESERVED	R	0h
82	I2C Controller NACKed	R/W	0h	Write 1 to clear the I2C Controller NACK event
81	Ready for Patch	R/W	0h	Write 1 to clear the patch bundle ready event
80	Patch Loaded	R/W	0h	Write 1 to clear the patch loaded event
79-67	RESERVED	R	0h
66	MBRD Buffer Ready	R/W	0h	Write 1 to clear the memory buffer full event
65	TX Memory Buffer Empty	R/W	0h	Write 1 to clear the transmit memory buffer empty event
64-61	RESERVED	R	0h
60	Liquid Detection	R/W	0h	Write 1 to clear the Liquid Detection state changed event
59-57	RESERVED	R	0h
56	Ext DCDC Sink Safe State	R/W	0h	Write 1 to clear the Power Role Swap accepted or Explicit PD Contract Accept received event
55-52	RESERVED	R	0h
51	Discover mode Completed	R/W	0h	Write 1 to clear the Discover Modes process completed event
50-47	RESERVED	R	0h
46	Unable to Source Error	R/W	0h	Write 1 to clear the Source unable to increase voltage to negotiated contract voltage event
45-44	RESERVED	R	0h
43	Plug Early Notification	R/W	0h	Write 1 to clear the connection detected but not yet debounced event
42	Sink Transition Completed	R/W	0h	Write 1 to clear the source power transition initiated event
41-40	RESERVED	R	0h
39	Message Data Error	R/W	0h	Write 1 to clear the erroneous message received event
38	Protocol Error	R/W	0h	Write 1 to clear the unexpected message received event
37	RESERVED	R	0h
36	Missing Get Capabalities Message Error	R/W	0h	Write 1 to clear the Port Partner Get_Sink_Cap or Get_Source_Cap no response event
35	Power Event Occurred Error	R/W	0h	Write 1 to clear the OVP, ILIM, or TSD on VBUS event
34	Can Provide Voltage or Current Later Error	R/W	0h	Write 1 to clear the Source power availability "Wait" event
33	Cannot Provide Voltage or Current Error	R/W	0h	Write 1 to clear the Source capability mismatch event
32	Device Incompatible Error	R/W	0h	Write 1 to clear the incompatible or non-USB PD capable Port Partner connected event
31	RESERVED	R	0h
30	CMD1 Complete	R/W	0h	Write 1 to clear the CMD1 command completed event
29	MIDB Received	R/W	0h	Write 1 to clear the Manufacturer Info message received event
28	RESERVED	R	0h
27	PD Status Updated	R/W	0h	Write 1 to clear the PD_STATUS (0x40) register contents changed event
26	Status Updated	R/W	0h	Write 1 to clear the STATUS (0x1A) register contents changed event
25	RESERVED	R	0h
24	Power Status Updated	R/W	0h	Write 1 to clear the POWER_STATUS (0x3F) register contents changed event
23	Power Path Switch Changed	R/W	0h	Write 1 to clear the POWER_PATH_STATUS (0x26) register contents changed event
22	RESERVED	R	0h
21	USB Host No Longer Present	R/W	0h	Write 1 to clear the UsbHostPresent field in the STATUS register transitioned to a value other than 11b event
20	USB Host Present	R/W	0h	Write 1 to clear the UsbHostPresent field in the STATUS register transitioned to 11b event
19-16	RESERVED	R	0h
15	Sink Cap Message Received	R/W	0h	Write 1 to clear the Sink Capabilities message received event
14	RESERVED	R	0h
13	New Contract as Provider	R/W	0h	Write 1 to clear the PD contract formed as Source event
12-10	RESERVED	R	0h
9	Overcurrent	R/W	0h	Write 1 to clear the Overcurrent field change event
8-4	RESERVED	R	0h
3	Plug Insert or Removal	R/W	0h	Write 1 to clear the USB Plug Status Changed event
2	RESERVED	R	0h
1	PD Hardreset	R/W	0h	Write 1 to clear the PD Hard Reset event
0	RESERVED	R	0h

6.1.9 Status Register (Offset = 1Ah) [Reset = 0000000020h]

Status is shown in Table 6-11.

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Status bit field for events.

Table 6-11 Status Register Field Descriptions

Bit	Field	Type	Reset	Description
39-26	RESERVED	R	0h
25-24	Acting as Legacy	R	0h	Indicates when PD Controller has gone into a mode where it is acting like a legacy (non PD) device. It can take approximately 10 seconds for the PD controller to determine that it is attached to a legacy source or sink. 0h = PD Controller is not in a legacy (non PD) mode 2h = PD Controller is acting like a legacy source
23-22	RESERVED	R	0h
21-20	VBUS Status	R	0h	Indicates the present state of VBUS. 0h = At vSafe0V (less than 0.8V) 1h = At vSafe5V (4.75V to 5.5V) 2h = Within expected limits 3h = Not within any of the other specified ranges
19-7	RESERVED	R	0h
6	Data Role	R	0h	PD controller data role. This is only valid once there is a connection. 0h = Upward-facing port (UFP) 1h = Downward-facing port (DFP)
5	Port Role	R	1h	Current state of PD Controller CCx terminations. This also indicates the PD Controller Power Role, once connected. This bit does not toggle during Unattached state transitions. 1h = PD Controller is Source (CCx pull-up active)
4	Plug Orientation	R	0h	Plug orientation indicator. Indicates port orientation when known (requires connection). 0h = Upside-up orientation (plug CC on CC1) 1h = Upside-down orientation (plug CC on CC2)
3-1	Connection State	R	0h	Details of a connected plug. 0h = No connection 1h = Port is disabled 2h = Corrosion Mitigaion (Ra/Ra) 3h = Debug connection (Rd/Rd) 4h = No connection Ra detected (Ra but no Rd) 5h = Debug connection (Rp/Rp) 6h = Connection present no Ra detected 7h = Connection present Ra detected
0	Plug Present	R	0h	Status of the plug 0h = No plug is connected 1h = A plug is connected

6.1.10 Power Path Status Register (Offset = 26h) [Reset = 0000000000h]

Power Path Status is shown in Table 6-12.

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Power Path Status. This is a hardware dependent register.

Table 6-12 Power Path Status Register Field Descriptions

Bit	Field	Type	Reset	Description
39-38	Power Source	R	0h	Indicates current PD Controller power source. 0h = Reserved 1h = PD Controller is powered from VIN_3V3 3h = Reserved
37-15	RESERVED	R	0h
14-12	PP3 Switch	R	0h	Indicates current state of PP3 (PP_EXT). 0h = PP3 switch disabled 1h = PP3 switch currently disabled due to fault 2h = PP3 switch enabled (system output)
11-9	RESERVED	R	0h
8-6	PP1 Switch	R	0h	Indicates current state of PP1 switch (PP5V). 0h = PP1 switch disabled 1h = PP1 switch currently disabled due to fault 2h = PP1 switch enabled (system output)
5-2	RESERVED	R	0h
1-0	PPCable1 Switch	R	0h	Indicates current state of PP_CABLE1 switch. 0h = PP_CABLE1 switch disabled 1h = PP_CABLE1 switch currently disabled 2h = PP_CABLE1 switch CC1 enabled (system output) 3h = PP_CABLE1 switch CC2 enabled (system output)

6.1.11 Global System Configuration Register (Offset = 27h) [Reset = 00000000000000000000000018101h]

Global System Configuration is shown in Table 6-13.

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Global system configuration (all ports). This register contains configuration bits that define hardware that is common to all ports and in most cases will not change in normal operation or will not require immediate action if changed. Any modifications to this register will cause a port disconnect and reconnect with the new settings. Initialized by Application Customization.

Table 6-13 Global System Configuration Register Field Descriptions

Bit	Field	Type	Reset	Description
115-19	RESERVED	R	0h
18-16	PP3 Config	R/W	1h	PP3 configuration. This register configures PP3 switch controls. 0h = PP3 not used and disabled 1h = PP3 is a Source (output)
15-14	ILIM Over Shoot	R/W	2h	PP_5V ILIM configuration. Controls the amount of overshoot used by the FW to select the current limit for the PP5V to VBUS. 0h = No additional overshoot margin 1h = Overshoot margin of at least 100 mA 2h = Overshoot margin of at least 200 mA 3h = Overshoot margin of at least 500 mA
13-11	RESERVED	R	0h
10-8	PP1 Config	R/W	1h	PP1 configuration (PP_5V). 0h = Not used (disabled) 1h = PP1 configured as source
7-1	RESERVED	R	0h
0	PP Cable1 Switch Config	R/W	1h	Enable PP_CABLE1. If this bit is asserted the PD controller will enable VCONN on PP_CABLE1 when required for USB specification compliance.

6.1.12 Port Configuration Register (Offset = 28h) [Reset = 000000000000000000000000000000220001h]

Port Configuration is shown in Table 6-14.

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Configuration for port-specific hardware. This register configures hardware that is specific for each port and in most cases will not change in normal operation or will not require immediate action if changed. Any modifications to this register will cause a port disconnect and reconnect with the new settings. Initialized by Application Customization.

Table 6-14 Port Configuration Register Field Descriptions

Bit	Field	Type	Reset	Description
143-136	iSense Offest	R/W	0h	Configure 0A voltage when bidrectional current sensor is used in the design. (14mv per LSB)
135-130	RESERVED	R	0h
129-128	Fixed PDO ILIM	R/W	0h	Added current offset for Fixed PDO Contract, used for modifying current offset for PD+BQ or PD+DCDC applications. 0h = 125mA 1h = 250mA 2h = 400mA 3h = 500mA
127-124	RESERVED	R	0h
123	Power Path	R/W	0h	Power Path depending on port, otherwise off 0h = Off 1h = PP3
122	ADC Pin	R/W	0h	ADC GPIO Pin 0h = GPIO0 1h = GPIO2
121-112	Gain (mV/A)	R/W	0h	Gain starting at 1mV/A (1mV/A per LSB as mV/A).
111-107	Sample Rate	R/W	0h	Sample rate starting at 10ms (10ms per LSB as ms).
106-104	IMON Factor	R/W	0h	IMON Factor starting at 100% (5% per LSB as %).
103-99	IMON Peak	R/W	0h	IMON Peak starting at 5A (1mA per LSB as mA).
98-96	ADC Shift	R/W	0h	ADC error shift. Range is 0 to 7
95-77	RESERVED	R	0h
76-74	Source UVP Threshold Selection	R/W	0h	Source UVP threshold Selection
73-31	RESERVED	R	0h
30-29	APDO ILIM Over Shoot	R/W	0h	Current limit overshoot for APDO contracts. Configures the current limit overshoot when power role is source and negotiated PD contract is variable type. This field is used to increase the current limit configuration of a supported BQ device. 0h = 25mA overshoot for APDO current 1h = 50mA above negotiated variable PDO current 2h = 75mA above negotiated variable PDO current 3h = Static 2900mA current limit
28-27	APDO VBUS UVP Threshold	R/W	0h	VBUS UVP threshold for APDO contracts. Configures the VBUS UVP threshold when power role is source and negotiated PDO contract is variable type. 0h = 90% below negotiated variable PDO voltage 1h = 88% below negotiated variable PDO voltage 2h = 92% below negotiated variable PDO voltage 3h = Reserved
26-22	RESERVED	R	0h
21-20	OVP for PP5V	R/W	2h	VBUS OVP settings while sourcing from PP1 (PP5V). See data-sheet for voltage range. 0h = Use setting 0: 5.25 V 1h = Use setting 1: 5.5 V 2h = Use setting 2: 5.8 V 3h = Use setting 3: 6.1 V
19-18	RESERVED	R	0h
17-16	VBUS OVP Usage	R/W	2h	OVP configuration settings. These two bits are used to select the OVP trip-point. The PD controller automatically computes the lowest threshold that does not overlap with the expected maximum voltage (including maximum tolerance allowed by USB PD specification). The OVP trip-point will be set at the selected percentage of the computed threshold. 0h = 100% 1h = 105% 2h = 111% 3h = 114%
15	RESERVED	R	0h
14-13	USB3 Rate	R/W	0h	USB3 configuration. 0h = USB3 not supported 1h = USB3 Gen1 signaling rate supported 2h = USB3 Gen2 signaling rate supported 3h = Reserved
12	DebugAccessory Support	R/W	0h	Assert this bit to enable DebugAccessory support.
11	USB Communication Capable	R/W	0h	Assert this bit in systems that are USB communications capable. This will be reported in the USB communcations capable field of PDO1.
10-2	RESERVED	R	0h
1-0	TypeC State machine	R/W	1h	Configuration of the Type-C State machine. This fields sets the default Type-C state of the PD controller. 1h = Source state machine only 3h = Reserved

6.1.13 Port Control Register (Offset = 29h) [Reset = 00015002h]

Port Control is shown in Table 6-15.

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Configuration bits affecting system policy. These bits may change during normal operation and are used for controlling the respective port. The PD Controller will not take immediate action upon writing. Changes made to this register will take effect the next time the appropriate policy is invoked. Initialized by Application Customization.

Table 6-15 Port Control Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R	0h
28-26	Charger Advertise Enable	R/W	0h	Configure the types of legacy chargers to emulate. 0h = BC 1.2 SDP only 1h = BC 1.2 CDP only 2h = BC 1.2 DCP only 3h = Reserved 4h = Reserved 5h = DCP Auto 1 (2.7V and DCP) 6h = DCP Auto 2 (1.2V 2.7V and DCP) 7h = Reserved
25	DCD Enable	R/W	0h	Enable for Data-Contact Detection. Assert this bit to enable Data Contact Detect as defined by BC 1.2 for sinks.
24	Resistor 15k Present	R/W	0h	Configure D+ and D- termination. Assert this bit if there is a 15kOhm pull-down on D+ and D- (USB2.0 Host Phy pull-downs enabled). This should not be used for DCP or DCP Auto modes. 0h = System does NOT have 15 kOhm pull-down 1h = System has 15 kOhm pull-down
23-21	RESERVED	R	0h
20	Enable Current Monitor	R/W	0h	Assert this bit to enable the PP5V current monitor (peak and average) that are read from the ADC_RESULTS register. While asserted the PD controller will remain in the active power mode.
19	Unconstrained Power	R/W	0h	Unconstrained Power configuration. This also sets the Unconstrained Power bit defined by USB PD. 0h = No unconstrained power 1h = Unconstrained power present
18-17	RESERVED	R	0h
16	Automatic ID Request	R/W	1h	Configure identity discovery for SOP. If this bit is asserted, the PD Controller will automatically issue Discover Identity VDM for all SOP types when appropriate.
15	Initiate Swap to DFP	R/W	0h	Configure DR_Swap to DFP initiation. If this bit is asserted, the PD Controller automatically initiates and sends DR_Swap requests to the Port Partner when appropriate if presently operating as UFP.
14	Process Swap to DFP	R/W	1h	Configure response to DR_Swap to DFP. If this bit is asserted, the PD Controller will automatically accept a DR_Swap request to become a DFP. Otherwise, the PD Controller will reject such a request.
13	Initiate Swap to UFP	R/W	0h	Configure DR_Swap to UFP initiation. If this bit is asserted, the PD Controller automatically initiates and sends DR_Swap requests to the Port Partner when appropriate if presently operating as DFP.
12	Process Swap to UFP	R/W	1h	Configure response to DR_Swap to UFP. If this bit is asserted, the PD Controller will automatically accept a DR_Swap request to become a UFP. Otherwise, the PD Controller will reject such a request.
11-2	RESERVED	R	0h
1-0	TypeC Current	R/W	2h	Type-C Current advertisement. This setting is ignored if a Source role is not enabled and active. This setting is also ignored during an explicit USB PD contract, where the Rp value is used for collision avoidance as required by the USB PD specification. Note that when PP5V is low, the FW will only use the default Type-C current regardless of the value in this field. 0h = USB Default Current 1h = 1.5 A 2h = 3.0 A 3h = Reserved

6.1.14 Boot Flags Register (Offset = 2Dh) [Reset = 0000000000h]

Boot Flags is shown in Table 6-16.

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Detailed status of boot process. This register provides details on PD Controller boot flags, Customer OTP configuration, and silicon revision

Table 6-16 Boot Flags Register Field Descriptions

Bit	Field	Type	Reset	Description
39-32	RESERVED	R	0h
31-29	Patch Config Source	R	0h	Source of patch configuration. This field indicates the source of the configuration patch that has been successfully loaded. 0h = No configuration has been loaded 5h = A configuration has been loaded from EEPROM 6h = A configuration has been loaded from I2C 7h = Reserved
28-20	RESERVED	R	0h
19	System TSD	R	0h	System thermal shut-down indicator. This bit is asserted if the PD controller is rebooting after the system thermal sensor caused a reset.
18	RESERVED	R	0h
17	PP3 Switch	R	0h	PP3 switch status. This bit is asserted when the PP3 sink path was enabled during dead-battery mode
16-14	RESERVED	R	0h
13	Region 1 CRC Fail	R	0h	Region 1 CRC status indicator. This bit is asserted when the CRC of data read from Region 1 of EEPROM memory failed.
12	Region 0 CRC Fail	R	0h	Region 0 CRC status indicator. This bit is asserted when the CRC of data read from Region 0 of EEPROM memory failed.
11	RESERVED	R	0h
10	Patch Download Error	R	0h	Asserted when a patch download error occurs.
9	Region 1 EEPROM Error	R	0h	Region 1 status indicator. This bit is asserted when an error occurred attempting to read Region 1 of EEPROM memory. A retry may have been successful.
8	Region 0 EEPROM Error	R	0h	Region 0 status indicator. This bit is asserted when an error occurred attempting to read Region 0 of EEPROM memory. A retry may have been successful.
7	Region 1 Invalid	R	0h	Region 1 header status indicator. This bit is asserted when Region 1 header of the EEPROM memory was invalid.
6	Region 0 Invalid	R	0h	Region 0 header status indicator. This bit is asserted when Region 0 header of the EEPROM memory was invalid.
5	Region 1	R	0h	Region 1 attempted indicator. This bit is asserted when Region 1 of the EEPROM memory was attempted.
4	Region 0	R	0h	Region 0 attempted indicator. This bit is asserted when Region 0 of the EEPROM memory was attempted.
3	I2C EEPROM Present	R	0h	EEPROM presence indicator. This bit is asserted when an EEPROM device was discovered during boot.
2-1	RESERVED	R	0h
0	Patch Header Error	R	0h	Asserted when a patch bundle header errors.

6.1.15 Received Sink Capabilities Register (Offset = 31h) [Reset = 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000h]

Received Sink Capabilities is shown in Table 6-17.

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Received Sink Capabilities. This register stores latest Sink Capabilities message received over BMC.

Table 6-17 Received Sink Capabilities Register Field Descriptions

Bit	Field	Type	Reset	Description
423-232	RESERVED	R	0h
231-200	Sink PDO 7	R	0h	Seventh Sink Capabilities PDO received
199-168	Sink PDO 6	R	0h	Sixth Sink Capabilities PDO received
167-136	Sink PDO 5	R	0h	Fifth Sink Capabilities PDO received
135-104	Sink PDO 4	R	0h	Fourth Sink Capabilities PDO received
103-72	Sink PDO 3	R	0h	Third Sink Capabilities PDO received
71-40	Sink PDO 2	R	0h	Second Sink Capabilities PDO received
39-8	Sink PDO 1	R	0h	First Sink Capabilities PDO received
7-3	RESERVED	R	0h
2-0	Number Valid PDOs	R	0h	Number of valid SPR PDOs in this register. Each PDO is 4 bytes. (max of 7)

6.1.16 Transmit Source Capabilities Register (Offset = 32h) [Reset = 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001h]

Transmit Source Capabilities is shown in Table 6-18.

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Source Capabilities for sending. This register stores PDOs and settings for outgoing Source Capabilities PD messages. Initialized by Application Customization.

Table 6-18 Transmit Source Capabilities Register Field Descriptions

Bit	Field	Type	Reset	Description
503-248	RESERVED	R	0h
247-216	TX Source PDO 7	R/W	0h	SPR Seventh Source Capabilities PDO contents.
215-184	TX Source PDO 6	R/W	0h	SPR Sixth Source Capabilities PDO contents.
183-152	TX Source PDO 5	R/W	0h	SPR Fifth Source Capabilities PDO contents.
151-120	TX Source PDO 4	R/W	0h	SPR Fourth Source Capabilities PDO contents.
119-88	TX Source PDO 3	R/W	0h	SPR Third Source Capabilities PDO contents.
87-56	TX Source PDO 2	R/W	0h	SPR Second Source Capabilities PDO contents.
55-24	TX Source PDO 1	R/W	0h	SPR First Source Capabilities PDO contents.
23-10	RESERVED	R	0h
9-8	Power Path for PDO 1	R/W	0h	Configures which PP to use for PDO1. 0h = PP5V is used for this PDO 2h = PP_EXT1 is used for this PDO
7-3	RESERVED	R	0h
2-0	Number Valid PDOs	R/W	1h	Number of valid PDOs in this register. Each PDO is 4 bytes. (max of 7)

6.1.17 Active PDO Contract Register (Offset = 34h) [Reset = 000000000000h]

Active PDO Contract is shown in Table 6-19.

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Power data object for active contract. This register stores PDO data for the current explicit USB PD contract, or all zeroes if no contract.

Table 6-19 Active PDO Contract Register Field Descriptions

Bit	Field	Type	Reset	Description
47-42	RESERVED	R	0h
41-32	First PDO Control Bits	R	0h	Contains PDO specific information of the first PDO. It does not matter which PDO was selected, this field is always drawn from the first PDO.
31-0	Active PDO	R	0h	Power data object. This field contains the contents of the PDO requested by PD controller as sink and accepted by source, once it is accepted by source.

6.1.18 Active RDO Contract Register (Offset = 35h) [Reset = 00000000000000000000000000000000h]

Active RDO Contract is shown in Table 6-20.

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Power data object for the active contract. This register stores the RDO of the current explicit USB PD contract, or all zeroes if no contract.

Table 6-20 Active RDO Contract Register Field Descriptions

Bit	Field	Type	Reset	Description
127-124	Requested Object Position	R	0h	Corresponding PDO location in the Source_Capabilities Message.
123	RESERVED	R	0h
122	Requested Capabality Missmatch	R	0h	Set when Source cannot satisfy the Sink's power or voltager requirements per Souce Capabilities
121	Requested USB Communication Capable	R	0h	When set, the device has USB data lines and is capable of communicating using USB2, USB3 or USB4 protocols
120	Requested No USB Suspend	R	0h	This flag is used to indicate what actions are taken in USB Suspend.
119	RequestedUnchunked Supported	R	0h	When set, the port supports chunked and unchucked messagse.
118-116	RESERVED	R	0h
115-106	Requested Operating Current	R	0h	Operating current (10mA per LSB)
105-96	Requested Max Min Operation Current	R	0h	Shall be assigned same as Operating Current field
95-32	RESERVED	R	0h
31-28	Object Position	R	0h	Corresponding PDO location in the Source_Capabilities Message.
27	Give Back Flag	R	0h	When set, the device will respond to a GotoMin message by reducing its load to minimum operating current
26	Capabality Missmatch	R	0h	Set when Source cannot satisfy the Sink's power or voltage requirements per Souce Capabilities
25	USB Communication Capable	R	0h	When set, the device has USB data lines and is capable of communicating using USB2, USB3 or USB4 protocols
24	No USB Suspend	R	0h	This flag is used to indicate what actions are taken in USB Suspend.
23	Unchunked Supported	R	0h	When set, the port supports chunked and unchucked messagse.
22-20	RESERVED	R	0h
19-10	Operating Current	R	0h	Operating current (10mA per LSB)
9-0	Max Min Operation Current	R	0h	Shall be assigned same as Operating Current field

6.1.19 Power Status Register (Offset = 3Fh) [Reset = 0000h]

Power Status is shown in Table 6-21.

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Details about the power of the connection. This register reports status regarding the power of the connection.

Table 6-21 Power Status Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h
9-8	Charger Advertise Status	R	0h	Charger Advertise Status 0h = Charger advertise disabled or not run 1h = Charger advertisement in process 2h = Charger advertisement complete 3h = Reserved
7-1	RESERVED	R	0h
0	Power Connection	R	0h	Asserted if there is a connection. This bit is asserted when STATUS.PlugPresent is TRUE AND STATUS.ConnState is greater than 5h. 0h = Connection requests power 1h = Connection provides power (PD Controller as sink) 3h = Explicit PD contract sets current

6.1.20 PD3 Configuration Register (Offset = 42h) [Reset = 00080010h]

PD3 Configuration is shown in Table 6-22.

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PD3.0 configuration settings.

Table 6-22 PD3 Configuration Register Field Descriptions

Bit	Field	Type	Reset	Description
31-21	RESERVED	R	0h
20	Support PPS Status	R/W	0h	Supports PPS Status Message. If this bit is asserted the PD controller will respond to a Get_PPS_Status message with the contents of the TX_PPS_SDB register (0x7A).
19	Support Get Revision	R/W	1h	Supports Revision Message. If this bit is asserted the PD controller will respond to a Get_Revision USB PD message with the supported PD Spec Version.
18	Support Get Source Info	R/W	0h	Support Source Info Message. If this bit is asserted the PD controller will respond to a Get_Source_Info USB PD message with the contents of TX_SOURCE_INFO (0x78) register.
17-13	RESERVED	R	0h
12	Support Manufacture Info Message	R/W	0h	Support Manufacturing Info message. If this bit is asserted the PD controller will respond to a Get_Manufacturer_Info USB PD message with the contents of the TX_MIDB_SOP register (0x73).
11	Support Battery Status Message	R/W	0h	Support Battery Status message. If this bit is asserted the PD controller will respond to a Get_Battery_Status USB PD message with the contents of the TX_BSDO register (0x7B).
10	Support Battery Capabilities Message	R/W	0h	Support Battery Capability message. If this bit is asserted the PD controller will respond to a Get_Battery_Capabilities USB PD message with the contents of the TX_BCDB register (0x7D).
9	RESERVED	R	0h
8	Support Source Extended Message	R/W	0h	Enable Source Capabilities Extended. If this bit is asserted the PD controller will respond to a Get_Source_Capabilities_Extended USB PD message with the contents of the TX_SCEDB register (0x77).
7	Auto Get MIDB	R/W	0h	Enable Auto send GetManufaturerInfo. If this bit is asserted, the PD controller will automatically send a Get_Manufacturer_Info USB PD msesage after receiving a Discovery_Identity USB PD message. The contents of the message will be stored in TX_MIBDB_SOP register (0x73)
6-5	RESERVED	R	0h
4	Unchunked Supported	R/W	1h	Enable unchunked support. If this bit is asserted the PD controller will support unchunked messaging (up to 260 bytes). The host is responsible to consume the unchunked message before the PD controller will be able to receive another long unchunked message.
3-0	RESERVED	R	0h

6.1.21 Received SOP Identity Data Object Register (Offset = 48h) [Reset = 00000000000000000000000000000000000000000000000000h]

Received SOP Identity Data Object is shown in Table 6-23.

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Received Discover Identity ACK (SOP). Latest Discover Identity response received over USB PD using SOP.

Table 6-23 Received SOP Identity Data Object Register Field Descriptions

Bit	Field	Type	Reset	Description
199-168	RX ID SOP VDO 6	R	0h	6th VDO. The sixth Data Object for Discover Identity response is context-specific.
167-136	RX ID SOP VDO 5	R	0h	5th VDO. The fifth Data Object for Discover Identity response is context-specific.
135-104	RX ID SOP VDO 4	R	0h	4th VDO. The fourth Data Object for Discover Identity response is context-specific as defined in USB PD.
103-72	RX ID SOP VDO 3	R	0h	Product VDO. The third Data Object for Discover Identity response.
71-40	RX ID SOP VDO 2	R	0h	Cert Stat VDO. The second Data Object for Discover Identity response.
39-8	RX ID SOP VDO 1	R	0h	ID Header VDO. The first Data Object in Discover Identity response.
7-6	Response Type	R	0h	Type of response received. 0h = SOP Discover Identity REQ not sent or pending 1h = Responder ACK received 2h = Responder NAK received or response timeout 3h = Responder BUSY received
5-3	RESERVED	R	0h
2-0	Number Valid VDOs	R	0h	Number of valid VDO's in this register. (Max of 6)

6.1.22 IO Config Register (Offset = 5Ch) [Reset = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000CCBh]

IO Config is shown in Table 6-24.

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Application-specific GPIO Configurations. This register cannot be modified at run-time, the GPIO configurations are set according to the configuration during the boot process.

Table 6-24 IO Config Register Field Descriptions

Bit	Field	Type	Reset	Description
391-384	GPIO 12 Mapped Event	R	0h	Event table mapping for GPIO12. See GPIO Event table.
383-376	GPIO 11 Mapped Event	R	0h	Event table mapping for GPIO11. See GPIO Event table.
375-368	GPIO 10 Mapped Event	R	0h	Event table mapping for GPIO10. See GPIO Event table.
367-352	RESERVED	R	0h
351-344	GPIO 7 Mapped Event	R	0h	Event table mapping for GPIO7. See GPIO Event table.
343-336	GPIO 6 Mapped Event	R	0h	Event table mapping for GPIO6. See GPIO Event table.
335-328	GPIO 5 Mapped Event	R	0h	Event table mapping for GPIO5. See GPIO Event table.
327-320	GPIO 4 Mapped Event	R	0h	Event table mapping for GPIO4. See GPIO Event table.
319-312	GPIO 3 Mapped Event	R	0h	Event table mapping for GPIO3. See GPIO Event table.
311-304	GPIO 2 Mapped Event	R	0h	Event table mapping for GPIO2. See GPIO Event table.
303-296	GPIO 1 Mapped Event	R	0h	Event table mapping for GPIO1. See GPIO Event table.
295-288	GPIO 0 Mapped Event	R	0h	Event table mapping for GPIO0. See GPIO Event table.
287-269	RESERVED	R	0h
268-256	GPIO Event Polarity	R	0h	Controls polarity of a selected output event for each GPIO. Assert the bit for a given GPIO to invert the polarity of the event mapped to it. This field has no impact for input GPIO Events.
255-230	RESERVED	R	0h
229	GPIO 5 Analog Input Control	R	0h	Assert when GPIO5 is used as an analog input. This must also be asserted when PORT_CONTROL.ChargerDetectEnable or ChargerAdvertiseEnable is non-zero.
228	GPIO 4 Analog Input Control	R	0h	Assert when GPIO4 is used as an analog input. This must also be asserted when PORT_CONTROL.ChargerDetectEnable or ChargerAdvertiseEnable is non-zero.
227	RESERVED	R	0h
226	GPIO AI Enable GPIO 2	R	0h	Assert when GPIO2 is used as an analog input.
225	RESERVED	R	0h
224	GPIO AI Enable GPIO 0	R	0h	Assert when GPIO0 is used as an analog input.
223-205	RESERVED	R	0h
204-192	Internal Pull Up Enable	R	0h	Controls weak pull-up setting for each configurable GPIO (1=Enabled, 0=Disabled).
191-173	RESERVED	R	0h
172-160	Internal Pull Down Enable	R	0h	Controls weak pull-down setting for each configurable GPIO (1=Enabled, 0=Disabled).
159-109	RESERVED	R	0h
108-96	Open Drain Output Enable	R	0h	Controls push-pull (0) vs. open-drain (1) setting for each configurable GPIO.
95-77	RESERVED	R	0h
76-64	Initial Value	R	0h	Controls default output level for each GPIO enabled as output (0=Drive Low, 1=Drive High)
63-45	RESERVED	R	0h
44-32	GPIO Interrupt Enable	R	0h	Controls interrupt enable for each GPIO (1=Interrupt Enabled, 0=Interrupt Disabled). Note that all GPIO pins may not be configured as inputs (see the data-sheet).
31-13	RESERVED	R	0h
12-0	GPIO Output Enable	R	CCBh	Controls output enable for each GPIO (1=Output Enabled, 0=Hi-Z). Note that all GPIO may not be configurable as an output (see data-sheet).

6.1.23 Type C State Register (Offset = 69h) [Reset = 00000000h]

Type C State is shown in Table 6-25.

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Contains current status of both CCn pins.

Table 6-25 Type C State Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	TypeC Port State	R	0h	Present state of Type-C state-machine. 0h = Disabled 5h = ErrorRecovery 24h = Unattached.Accessory 2Bh = AttachWait.Accessory 45h = Try.SRC 50h = TryWait.SRC 60h = Attached.SRC 62h = CorrosionMitigation 63h = DebugAccessory 64h = AttachWait.SRC 67h = Unattached.SRC
23-16	CC2 Pin State	R	0h	State of CC2 pin 0h = Not connected 1h = Ra detected (Source only) 2h = Rd detected (Source only)
15-8	CC1 Pin State	R	0h	State of CC1 pin 0h = Not connected 1h = Ra detected (Source only) 2h = Rd detected (Source only)
7-0	CC Pin for PD	R	0h	CC pin used for PD communication. 0h = Not connected 1h = CC1 is used for USB PD communication 2h = CC2 is used for USB PD communication

6.1.24 ADC Results Register (Offset = 6Ah) [Reset = 00000000000000000000000000h]

ADC Results is shown in Table 6-26.

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Provides access to measurements from the internal ADC. The PD controller periodically measures the pins mentioned in this register and updates the register accordingly. The frequency of the update depends upon the mode of the PD controller. For example, in Unconnected Sleep the PD controller will not update these registers. This register should only be used for debug purposes and not for end solutions.

Table 6-26 ADC Results Register Field Descriptions

Bit	Field	Type	Reset	Description
103-96	RESERVED	R	0h
95-88	IVBUS_Peak	R	0h	Most recent current peak estimate through poewr path. If PORT_CONTROL.EnableCurrentMonitor = 1, this field is an estimate of the recent peak current. It is cleared upon attach for a new connection.(16.5mA per LSB)
87-80	GPIO2	R	0h	Most recent voltage on the GPIO2 pin. (14mV per LSB)
79-72	GPIO0	R	0h	Most recent voltage on the GPIO0 pin. (14mV per LSB)
71-64	GPIO5	R	0h	Most recent voltage on the GPIO5 pin. (14mV per LSB)
63-56	GPIO4	R	0h	Most recent voltage on the GPIO4 pin. (14mV per LSB)
55-48	RESERVED	R	0h
47-40	IVBUS_Mean	R	0h	Most recent current mean estimate through power path. If PORT_CONTROL.EnableCurrentMonitor = 1, this field is an estimate of the recent mean current. It is cleared upon attach for a new connection.(16.5mA per LSB)
39-32	RESERVED	R	0h
31-24	VBUS	R	0h	Most recent voltage on the VBUS pin. (98mV per LSB)
23-16	LDO3V3	R	0h	Most recent voltage on the LDO_3V3 pin. (14mV per LSB)
15-8	ADCIN2	R	0h	Most recent voltage on the ADCIN2 pin. (14mV per LSB)
7-0	ADCIN1	R	0h	Most recent voltage on the ADCIN1 pin. (14mV per LSB)

6.1.25 Sleep Control Register (Offset = 70h) [Reset = 03h]

Sleep Control Register is shown in Table 6-27.

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Sleep configurations.

Table 6-27 Sleep Control Register Field Descriptions

Bit	Field	Type	Reset	Description
7-3	RESERVED	R	0h
2-1	Sleep Time	R/W	1h	Minimum time the PD controller waits before entering sleep mode. 0h = Reserved 1h = 100 ms 2h = 1000 ms 3h = Reserved
0	Sleep Mode Allowed	R/W	1h	If this bit is asserted the PD controller will enter sleep modes after device is idle for Sleep Time.

6.1.26 GPIO Status Register (Offset = 72h) [Reset = 0000000000000000h]

GPIO Status is shown in Table 6-28.

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Captures status and settings of all GPIO pins. Check the device-specific datasheet for the available GPIO because it may vary by device type.

Table 6-28 GPIO Status Register Field Descriptions

Bit	Field	Type	Reset	Description
63-40	RESERVED	R	0h
39	GPIO 7 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
38	GPIO 6 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
37	GPIO 5 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
36	GPIO 4 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
35	GPIO 3 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
34	GPIO 2 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
33	GPIO 1 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
32	GPIO 0 Direction	R	0h	This bit is asserted when this GPIO is configured as an output.
31-13	RESERVED	R	0h
12	GPIO 12 Data	R	0h	Asserted if a logic high is detected on the GPIO.
11	GPIO 11 Data	R	0h	Asserted if a logic high is detected on the GPIO.
10	GPIO 10 Data	R	0h	Asserted if a logic high is detected on the GPIO.
9-8	RESERVED	R	0h
7	GPIO 7 Data	R	0h	Asserted if a logic high is detected on the GPIO.
6	GPIO 6 Data	R	0h	Asserted if a logic high is detected on the GPIO.
5	GPIO 5 Data	R	0h	Asserted if a logic high is detected on the GPIO.
4	GPIO 4 Data	R	0h	Asserted if a logic high is detected on the GPIO.
3	GPIO 3 Data	R	0h	Asserted if a logic high is detected on the GPIO.
2	GPIO 2 Data	R	0h	Asserted if a logic high is detected on the GPIO.
1	GPIO 1 Data	R	0h	Asserted if a logic high is detected on the GPIO.
0	GPIO 0 Data	R	0h	Asserted if a logic high is detected on the GPIO.

6.1.27 TX Manufactrer Info SOP Register (Offset = 73h) [Reset = 00000000000000000000000000000000000000000000h]

TX Manufactrer Info SOP is shown in Table 6-29.

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Transmit Manufacturer Info Data Block SOP (MIDB). The host must enable this feature using the SupportManufacturerInfoMsg bit in the PD3 Configuration register (0x42). If the SupportManufacturerInfoMsg bit is set to 0, then when a Get_Manufacturer_Info message is received the PD controller responds with a Not_Supported message. If the SupportManufacturerInfoMsg bit is set to 1, then the PD controller responds to a Get_Manufacturer_Info message with a target specified as "Port". If received Get_Manufacturer_Info message has a target specified as "Battery", then the PD controller responds by appending the ASCII string "Not Supported" followed by a zero byte.

Table 6-29 TX Manufactrer Info SOP Register Field Descriptions

Bit	Field	Type	Reset	Description
175-0	Manufacturer String	R/W	0h	Manufacturer String as defined in USB PD. This must be a null terminated string. The PD controller always sends all 22 bytes.

6.1.28 Tx Source Capabilities Extended Data Block Register (Offset = 77h) [Reset = 000000000000000000000000000000h]

Tx Source Capabilities Extended Data Block is shown in Table 6-30.

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Transmit Source Capabilities Extended Data Block (SCEDB). If the PD3 configuration register (0x42) bit SourceCapExtMsg is set to zero, the PD controller responds to a Get_Source_Cap_Extended USB PD message with a Not_Supported message. If the SourceCapExtMsg bit is set to 1 then the response is generated from the contents of this register based on USB PD requirements. The VID, PID, and XID fields are taken from the PD internal firmware configurable through the Application Customization Tool, the FW version is taken from the PD internal firmware, then the contents of this register are appended.

Table 6-30 Tx Source Capabilities Extended Data Block Register Field Descriptions

Bit	Field	Type	Reset	Description
119-111	RESERVED	R	0h
110-104	Source PDP	R/W	0h	Source's PDP rating as defined by the USB PD specification.
103-100	Number Hot Swappable Batteries	R/W	0h	Number of hot swappable batteries / battery slots as defined by the USB PD specification. (Max of 4)
99-96	Number Fixed Batteries	R/W	0h	Number of fixed batteries / battery slots as defined by the USB PD specification. (Max of 4)
95-88	Source Inputs	R/W	0h	Source inputs as defined by the USB PD specification.
87-80	Touch Temperature	R/W	0h	Touch temperature as defined by the USB PD specification.
79-64	Peak Current 3	R/W	0h	Peak Current 3 as defined by the USB PD specification.
63-48	Peak Current 2	R/W	0h	Peak Current 2 as defined by the USB PD specification.
47-32	Peak Current 1	R/W	0h	Peak Current 1 as defined by the USB PD specification.
31-24	Touch Current	R/W	0h	Touch current as defined by the USB PD specification.
23-16	Compliance	R/W	0h	Compliance as defined by the USB PD specification.
15-8	Hold Up Time	R/W	0h	Hold up time as defined by the USB PD specification.
7-0	Voltage Regulation	R/W	0h	Voltage regulation as defined by the USB PD specification.

6.1.29 TX Source Info Register (Offset = 78h) [Reset = 8000000080000000h]

TX Source Info is shown in Table 6-31.

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Transmit Source info. If the PD3 configuration register (0x42) bit SupportGetSourceInfo is set to 0 and a Get_Source_Info message is received, then this register is ignored and the PD controller sends a Not_Supported message. If the SupportGetSourceInfo bit is set to 1 and a Get_Source_Info message is received then the contents of this register are sent in response. This register is automatically updated by the PD firmware and does not require any EC implementation.

Table 6-31 TX Source Info Register Field Descriptions

Bit	Field	Type	Reset	Description
63	PortType	R/W	1h	Managed or Guaranteed Capability Port: Managed = 0, Guaranteed = 1
62	DPSPort	R/W	0h	DPS Port. If set, then PortType shall be 0 (Managed Capability Port)
61-50	RESERVED	R	0h
49-41	Port Maximum PDP 0.5W	R/W	0h	Maximum power the port will provide in 0.5W steps. (0.5W per LSB)
40-32	Port Guaranteed PDP 0.5W	R/W	0h	Minimum power the port is ensured to always be able to provide in 0.5W steps. (0.5W per LSB)
31	Port Type	R/W	1h	Managed or Guaranteed Capability Port: Managed = 0, Guaranteed = 1
30-24	RESERVED	R	0h
23-16	Port Maximum PDP	R/W	0h	Power the port is designed to supply. (1W per LSB)
15-8	Port Present PDP	R/W	0h	Power the port is presently capable of supplying. (1W per LSB)
7-0	Port Reported PDP	R/W	0h	Power the port is actually advertising. (1W per LSB)

6.1.30 Transmitted PPS Status Data Block Register (Offset = 7Ah) [Reset = 00000000h]

Transmitted PPS Status Data Block is shown in Table 6-32.

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Transmit PPS Status Data Block (BSDO). If the PD3 configuration register (0x42) bit SupportPPSStatus is set to zero and a Get_PPS_Status message is received, then this register is ignored and the PD controller sends a Not_Supported message. If the SupportPPSStatus bit is set to 1 and a Get_PPS_Status message is received then the contents of this register are sent in response.

Table 6-32 Transmitted PPS Status Data Block Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R	0h
27	OMF	R/W	0h	Operating Mode Flag (OMF), indicates if running in Constant Voltage (CV - 0b) or Current Limit (CL - 1b) mode.
26-25	PTF	R/W	0h	Present Temperature Flag (PTF), indicates if temperature is normal (01b), warning zone (10b), or over-temperature (11b).
24	RESERVED	R	0h
23-16	Output Current	R/W	0h	Output current as defined by the USB PD spec. (50mA per LSB). 0xFF = this field not supported
15-0	Output Voltage	R/W	0h	Output voltage as defined by the USB PD spec.(20mV per LSB, 0xFFFF = this field not supported)

6.1.31 Transmitted Battery Status Data Objects (BSDO) Register (Offset = 7Bh) [Reset = 000000000000000000000000FFFF0200h]

Transmitted Battery Status Data Objects (BSDO) Register is shown in Table 6-33.

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Transmit Battery Status Data Objects (BSDO). The host should also program the Tx Source Capabilities Extended register (0x77) in order to specify the number of each type of battery such that it is consistent with the contents of this register. This feature must be enabled in the PD3_CONFIG register (0x42) SupportBatteryStatusMsg bit. The PD controller does not take any automatic action if this register is written. If the SupportBatteryStatusMsg bit is set to 0 and a Get_Battery_Status message is received, then this register is ignored and the PD controller sends a Not_Supported message. If the SupportBatteryStatusMsg bit is set to 1, and a Get_Battery_Status message is received then the contents of this register are sent in response.

Table 6-33 Transmitted Battery Status Data Objects (BSDO) Register Field Descriptions

Bit	Field	Type	Reset	Description
127-112	Battery 3 Present Info	R/W	0h	Battery status data object returned for battery index 3.
111-104	Battery 3 Battery Info	R/W	0h	Battery status data object returned for battery index 3.
103-96	RESERVED	R	0h
95-80	Battery 2 Present Capacity	R/W	0h	Battery status data object returned for battery index 2.
79-72	Battery 2 Battery Info	R/W	0h	Battery status data object returned for battery index 2.
71-64	RESERVED	R	0h
63-48	Battery 1 Present Capacity	R/W	0h	Battery status data object returned for battery index 1.
47-40	Battery 1 Battery Info	R/W	0h	Battery status data object returned for battery index 1.
39-32	RESERVED	R	0h
31-16	Battery 0 Present Capacity	R/W	FFFFh	Battery status data object returned for battery index 0.
15-8	Battery 0 Battery Info	R/W	2h	Battery status data object returned for battery index 0.
7-0	RESERVED	R	0h

6.1.32 Tx Battery Capabilities Register (Offset = 7Dh) [Reset = 000000000000000000000000000000000000000000000000000000000000000000000000h]

Tx Battery Capabilities is shown in Table 6-34.

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Transmit Battery Capability Data Block (BCDB). The host should also program the Tx Source Capabilities Extended register (0x77) in order to specify the number of each type of battery such that it is consistent with the contents of this register. This feature must be enabled in the PD3_CONFIG register (0x42) bit SupportBatteryCapMsg. The PD controller does not take any automatic action if this register is written. If the SupportBatteryCapMsg is 0 and a Get_Battery_Capabilities message is received, then the contents of this register are ignored and the PD controller sends a Not_Supported message. If the SupportBatteryCapMsg is 1 and a Get_Battery_Capabilities message is received, then the contents of this register are sent in response.

Table 6-34 Tx Battery Capabilities Register Field Descriptions

Bit	Field	Type	Reset	Description
287-280	Battery Type	R/W	0h	Battery type for battery index 0.
279-264	Battery Last Full Charge Capacity	R/W	0h	Battery last full charge capacity for battery index 0.
263-248	Battery Design Capacity	R/W	0h	Battery design capacity for battery index 0.
247-232	PID 3	R/W	0h	PID for battery index 0.
231-216	VID 3	R/W	0h	VID for battery index 0.
215-208	Battery Type	R/W	0h	Battery type for battery index 2.
207-192	Battery Last Full Charge Capacity	R/W	0h	Battery last full charge capacity for battery index 2.
191-176	Battery Design Capacity	R/W	0h	Battery design capacity for battery index 2.
175-160	PID 2	R/W	0h	PID for battery index 2.
159-144	VID 2	R/W	0h	VID for battery index 2.
143-136	Battery Type	R/W	0h	Battery type for battery index 1.
135-120	Battery Last Full Charge Capacity	R/W	0h	Battery last full charge capacity for battery index 1.
119-104	Battery Design Capacity	R/W	0h	Battery design capacity for battery index 1.
103-88	PID 1	R/W	0h	PID for battery index 1.
87-72	VID 1	R/W	0h	VID for battery index 1.
71-64	Battery Type	R/W	0h	Battery type for battery index 0.
63-48	Battery Last Full Charge Capacity	R/W	0h	Battery last full charge capacity for battery index 0.
47-32	Battery Design Capacity	R/W	0h	Battery design capacity for battery index 0.
31-16	PID 0	R/W	0h	PID for battery index 0.
15-0	VID 0	R/W	0h	VID for battery index 0.

6.1.33 Liquid Detection Configuration Register (Offset = 98h) [Reset = 0000000000000052000000h]

Liquid Detection Configuration is shown in Table 6-35.

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Liquid Detection Configuration

Table 6-35 Liquid Detection Configuration Register Field Descriptions

Bit	Field	Type	Reset	Description
87-80	Pulldown Threshold ADC	R/W	0h	Additional threshold check for pulldown resistor modifying threshold (e.g. RA in cable) (14mV per LSB as mV)
79	RESERVED	R	0h
78	Single Pin Monitoring	R/W	0h	When enabled, only single LD pin is used for detection
77-76	Liquid Pins to Monitor	R/W	0h	Determine pins to monitor during liquid detection. 0 = UnusedPins (SBU), 1 = CC, 2= DPDM, 3= RSVD
75	Monitor During Unattach	R/W	0h	Monitor for liquid detection while unattached to a device.
74	Monitor During Attach	R/W	0h	Monitor for liquid detection while attached to a device. This may not be set if CC pins are used for liquid detection.
73	Enable Corrosion Mitigation	R/W	0h	Enable corrosion mitigation. Corrosion mitigation will disconnect the port, disable the port, and pull down CC pins. Type-C error-recovery will be triggered when the port transitions to no-moisture state.
72	Enable Liquid Detection	R/W	0h	Enables liquid detection on the pins connected to the GPIO on the PD Controller. In order for this to function correctly the proper external liquid detection circuitry must be in place.
71-64	High Threshold ADC Liquid	R/W	0h	High Threshold ADC Liquid (14mV per LSB as mV)
63-56	Low Threshold ADC Liquid	R/W	0h	Low Threshold ADC Liquid (14mV per LSB as mV)
55-48	High Threshold ADC No Liquid	R/W	0h	High Threshold ADC No Liquid, provides hysteresis for exit out of Liquid Detected. (14mV per LSB as mV)
47-40	Low Threshold ADC No Liquid	R/W	0h	Low Threshold ADC No Liquid, provides hysteresis for exit out of Liquid Detected. (14mV per LSB as mV)
39-32	Number of Samples	R/W	0h	Number of samples used for averaging. Valid values must be powers of two (1, 2, 4, 8, ...)
31-28	Liquid Detection Retries	R/W	5h	Number of times to retry checking for liquid on a port. Must be set to greater than 2 for CC liquid detection.
27-24	Liquid Detection Retries Wait Time	R/W	2h	Time to wait between retrying checking for liquid on a port. Must be set to at least 100ms for CC liquid detection. (100ms per LSB as ms)
23-20	Sample Time in 10ms Liquid	R/W	0h	Sample Time in multiples of 10ms (10ms per LSB as ms)
19-16	Sample Time in 10ms Non-Liquid	R/W	0h	Sample Time in multiples of 10ms (10ms per LSB as ms)
15-8	Wait Time In Sec Liquid	R/W	0h	Wait in multiples of 1s when liquid is detected (1000ms per LSB as ms)
7-0	Wait Time In Sec Non-Liquid	R/W	0h	Wait in multiples of 1s when liquid is not detected. (1000ms per LSB as ms)

6.1.34 Rx MIDB Register (Offset = A4h) [Reset = 00000000000000000000000000000000000000000000h]

Rx MIDB is shown in Table 6-36.

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This register stores the manufacturer info received after sending a Get_Manufacturer_Info PD Message

Table 6-36 Rx MIDB Register Field Descriptions

Bit	Field	Type	Reset	Description
175-0	Manufactuer Info	R	0h	The received manufacturer info message.

6.1.35 Liquid Detection STATUS Register (Offset = B2h) [Reset = 0000000000h]

Liquid Detection STATUS Register is shown in Table 6-37.

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Table 6-37 Liquid Detection STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
39-32	Liquid Detected High Measurement	R	0h	LD1 ADC measurement when GPIO is driving circuit to VDD. (14mV per LSB as mV)
31-24	Liquid Detected Low Measurment	R	0h	LD1 ADC measurment when GPIO is driving circuit to GND. (14mV per LSB as mV)
23-16	No Liquid Detected High Measurement	R	0h	LD0 ADC measurement when GPIO is driving circuit to VDD. (14mV per LSB as mV)
15-8	No Liquid Detected Low Measurment	R	0h	LD0 ADC Measurement when GPIO is driving circuit to GND. (14mV per LSB as mV)
7	Liquid Measurment Status	R	0h	Indicates liquid detection measurment is currently ongoing on the device.
6-3	Liquid Retry Count	R	0h	Number of times liquid detection has been completed.
2	Mitigation Status	R	0h	Indicates port is currently in corrosion mitigation and will not attach to a device.
1	Liquid Status State	R	0h	Indicates liquid has been detected on the port at least LQDRetries number of times.
0	Liquid Detection State	R	0h	Indicates if liquid was seen on the port during the current measurement.