SPMU381A April   2026  – August 2026 TPS25752A

 

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  2. 1Read This First
    1. 1.1 Notational Conventions
    2. 1.2 Glossary
    3. 1.3 Related Documents
    4. 1.4 Support Resources
    5. 1.5 Trademarks
  3. 2Introduction
    1. 2.1 Purpose and Scope
  4. 3PD Controller Host Interface Description
    1. 3.1 Overview
    2. 3.2 Register and Field Notation
  5. 4Unique Address Interface
    1. 4.1 Unique Address Interface Protocol
  6. 5PD Controller Policy Modes
    1. 5.1 Overview
    2. 5.2 Source Policy Mode
  7. 6Register Overview
    1. 6.1 TPS25752A Registers
  8. 74CC Task Detailed Descriptions
    1. 7.1 Overview
    2. 7.2 CPU Control Tasks
      1. 7.2.1 'Gaid' - Return to Normal Operation
      2. 7.2.2 'GAID' - Cold Reset Request
    3. 7.3 PD Message Tasks
      1. 7.3.1 'SWDF' - PD DR_Swap to DFP
      2. 7.3.2 'SWUF' - PD DR_Swap to UFP
      3. 7.3.3 'GSkC' - PD Get Sink Capabilities
      4. 7.3.4 'SSrC' - PD Send Source Capabilities
      5. 7.3.5 'GPPI' - PD Get Port Partner Information
      6. 7.3.6 'MBRd' - Message Buffer Read
    4. 7.4 Patch Bundle Update Tasks
      1. 7.4.1 'PBMs' - Start Patch Burst Mode Download Sequence
      2. 7.4.2 'PBMc' - Patch Burst Mode Download Complete
      3. 7.4.3 'PBMe' - End Patch Burst Mode Download Sequence
      4. 7.4.4 'FLrd' - Flash Memory Read
      5. 7.4.5 'FLad' - Flash Memory Write Start Address
      6. 7.4.6 'FLwd' - Flash Memory Write
      7. 7.4.7 'FLvy' - Flash Memory Verify
    5. 7.5 System Tasks
      1. 7.5.1 'I2Cr' - I2C Read Transaction
      2. 7.5.2 'I2Cw' - I2C Write Transaction
      3. 7.5.3 'GPsh' - set GPIO high
      4. 7.5.4 'GPsl' - set GPIO low
  9. 8User Reference
    1. 8.1 PD Controller Application Customization
    2. 8.2 Loading a Patch Bundle
    3. 8.3 Liquid Detection Registers
    4. 8.4 GPIO Events
  10. 9Revision History

7.5.1 'I2Cr' - I2C Read Transaction

Table 7-17 'I2Cr' - Executes I2C Read Transaction on I2Cc
DescriptionThe 'I2Cr' task can be used to cause the PD controller to read from a specified target address and register offset using a I2C read transaction through the I2Cc_SDA and I2Cc_SCL pins.
INPUT DATAXBitNameDescription
Byte 3: Number of bytes to read from the target.
7:0NumBytes
Byte 2: Register offset to use in the I2C read transaction.
7:0RegisterOffset
Byte 1: Target Address
7Reserved
6:0Target to use for the transaction.
OUTPUT DATAXBitNameDescription
Bytes 2-65: Data Bytes read from the target (in order received)
511:0Data
Byte 1: Standard Task Return Code. See also Table 7-1.
Task CompletionThe PD controller completes after it has successfully read the specified number of bytes, or the I2C transaction terminated for some other reason.
Side EffectsThis task causes the PD controller to issue a command on the I2Cc port. It can result in INT_EVENTx.I2CControllerNACKed being asserted.
Additional InformationThe 'I2Cr' command cannot be sent within 150ms from sending a previous 'I2Cr' command. This allows the PD controller to complete all I2C transactions.