SPRACV1B February   2022  – January 2024 AM2434 , AM6411 , AM6412 , AM6421 , AM6441 , AM6442

 

  1.   Abstract
  2.   2
  3.   Trademarks
  4. 1Introduction
  5. 2Processor Core Benchmarks
    1. 2.1 Dhrystone
    2. 2.2 Trigonometric Functions
  6. 3Compute and Memory System Benchmarks
    1. 3.1 Memory Bandwidth and Latency
      1. 3.1.1 LMBench
      2. 3.1.2 STREAM
      3. 3.1.3 Cortex-R5 Memory Access Latency
    2. 3.2 CoreMark®-Pro
    3. 3.3 Fast Fourier Transform
    4. 3.4 Cryptographic Benchmarks
  7. 4Application Benchmarks
    1. 4.1 Machine Learning Inference
    2. 4.2 Field Oriented Control (FOC) Loop
    3. 4.3 PCIE to DDR Performance Using BCDMA
      1. 4.3.1 Test Setup
      2. 4.3.2 Result and Observation
    4. 4.4 DDR to DDR Performance Using BCDMA
      1. 4.4.1 Test Setup
      2. 4.4.2 Result and Observation
  8. 5References
  9. 6Revision History

4.4.2 Result and Observation

This section provides test results and observation for DDR to DDR data copy using UDMA channels.

Buffer Size (Bytes)
  • DDR to DDR (UDMA)Transfer BW (Mbits/sec)
1 BCDMA Channel 2 BCDMA Channels 4 BCDMA Channels 8 BCDMA Channels 16 BCDMA Channels
1 1.143 1.6 2.13 2.06 1.80
2 5.33 6.4 5.33 4.74 3.88
4 8 12.8 10.67 9.85 7.88
8 16 21.33 23.27 18.96 15.51
16 42.67 42.67 46.54 39.38 31.51
32 85.33 85.33 93.09 75.85 63.01
64 170.67 204.8 170.67 157.54 124.12
128 256 341.33 341.33 341.33 282.48
256 512 585.14 630.15 655.36 555.39
512 1024 1170.28 1489.45 1424.69 1285.02
1024 1638.4 2048 2730.67 2520.61 2520.61
2048 2340.57 2978.91 3640.89 4369.07 3236.34
4096 3276.8 4369.07 4681.14 5041.23 3615.78
8192 4096 5698.79 4946.11 4946.11 4017.53
16384 4681.14 6898.52 5140.08 5190.97 4136.39
32768 4946.11 7710.12 5322.72 5165.40 4181.76

Figure 4-6 shows the DDR to DDR read performance curve using BCDMA channels.

The 1 BCDMA channel is being referred to as 1 TRPD.

Data shown here range from 40B to 1600B for clear visualization purpose.

GUID-6902C7C9-5413-499B-B115-6C716B862D81-low.png Figure 4-6 DDR Performance Graph

Observation:

Maximum throughput is achieved with 4 parallel DMA transfers, further adding of channels will work but will not increase throughput.