SPRAD32 May   2022 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2AM26x FOC ISR Benchmarks
  4. 3Typical Application Scenarios for Traction Inverters
    1. 3.1 Sample ADC in Cycle 0 and Update PWM in Cycle 1
    2. 3.2 Sample ADC in First Half of Cycle 0 and Update PWM in Second Half of Cycle 0
  5. 4Summary
  6. 5References

4 Summary

As discussed in previous sections, an AM263x traction inverter demo is optimized with O3 from TI Clang v1.3.0.LTS. It takes a 400 MHz R5F core 3.9 µs to run from the start of ADC sample to the end of PWM update. There are decent amount of time left on the same core for customized operations. And, there are another one R5F in the same cluster for dual mode configuration, and another cluster of R5F cores for either dual mode or lock step mode. If all cores are in dual mode, there are 400 µs CPU time available in a 100 µs PWM cycle. The 3.9 µs is event less than 1% of the 400 µs total CPU time.

Given the nature of traction inverter, the other cluster would probably be configured in lock step mode for AutoSAR, and other R5F in the same cluster could be used as a safety monitor. With this assumption, in the case of 20 kHz PWM, 20 kHz resolver, and updating twice in one PWM cycle, 3.9 µs is only 15.6% of the traction core usage and there is 44% of CPU time available if a 60% limit is set for control loop interrupt service routine in one core.

After all, AM263x family of devices is a powerful platform for traction inverters.