Product details

TI.com inventory 0 Frequency (MHz) 400 RAM (KB) 2048 ADC 12-bit SAR GPIO 140 UART 6 Operating temperature range (C) -40 to 105 Ethernet MAC only
TI.com inventory 0 Frequency (MHz) 400 RAM (KB) 2048 ADC 12-bit SAR GPIO 140 UART 6 Operating temperature range (C) -40 to 105 Ethernet MAC only
NFBGA (ZCZ) 324

Processor Cores:

  • Single, dual, and quad-core Arm Cortex-R5F MCU with each core running up to 400 MHz
    • 16KB I-cache with 64-bit ECC per CPU core
    • 16KB D-cache with 32-bit ECC per CPU core
    • 64KB Tightly-Coupled Memory (TCM) with 32-bit ECC per CPU core
    • Lockstep or Dual-core capable clusters

Memory Subsystem:

  • 2MB of On-Chip RAM (OCSRAM)
    • 4 Banks x 512KB
    • ECC error protection
    • Internal DMA engine support

System on Chip (SoC) Services and Architecture:

  • 1x EDMA to support data movement functions
  • Device Boot supported from the following interfaces:
    • UART (Primary/Backup)
    • QSPI NOR Flash (4S/1S) (Primary)
  • Interprocessor communication modules
    • SPINLOCK module for synchronizing processes running on multiple cores
    • MAILBOX functionality implemented through CTRLMMR registers
  • Central Platform Time Sync (CPTS) support with time-sync and compare-event interrupt routers

Media and Data Storage:

  • 1x 4-bit Multi-Media Card/Secure Digital (MMC/SD) interface
  • General-Purpose Memory Controller (GPMC)
    • 16-bit parallel data bus with 22-bit address bus
    • Up to 4MB addressable memory space
    • Integrated Error Location Module (ELM) support for error checking

General Connectivity:

  • 6x Universal Asynchronous RX-TX (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 5x Local Interconnect Network (LIN) ports
  • 4x Inter-Integrated Circuit (I2C) ports
  • 4x Modular Controller Area Network (MCAN) modules with CAN-FD support
  • 1x Quad Serial Peripheral Interface (QSPI)
  • 4x Fast Serial Interface Transmitters (FSITX)
  • 4x Fast Serial Interface Receivers (FSIRX)
  • Up to 140 General-Purpose I/O (GPIO) pins

Sensing & Actuation:

  • Real-time Control Subsystem (CONTROLSS)
  • Flexible Input/Output Crossbars (XBAR)
  • 5x 12-bit Analog-to-Digital Converters (ADC)
    • 6-input SAR ADC up to 4 MSPS
      • 6x Single-ended channels OR
      • 3x Differential channels
    • Highly Configurable ADC Digital Logic
      • XBAR Start of Conversion Triggers (SOC)
      • User-defined Sample and Hold (S+H)
      • Flexible Post-Processing Blocks (PPB)
  • 10x Analog Comparators with Type-A programmable DAC reference (CMPSSA)
  • 10x Analog Comparators with Type-B programmable DAC reference (CMPSSB)
  • 1x 12-bit Digital-to-Analog Converter (DAC)
  • 32x Pulse Width Modulation (EPWM) modules
    • Single or Dual PWM channels
    • Advanced PWM Configurations
    • Extended HRPWM time resolution
  • 10x Enhanced Capture (ECAP) modules
  • 3x Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2x 4-Ch Sigma-Delta Filter Modules (SDFM)
  • Additional Signal-multiplex Crossbars (XBAR)

Industrial Connectivity:

  • Programmable Real-Time Unit (PRU-SS) and PRU-Industrial Communication Subsystem (PRU-ICSS)
    • Dual core Programmable Realtime Unit Subsystem (PRU0 / PRU1)
      • Deterministic Hardware
      • Dynamic Firmware
    • 20-channel enhanced input (eGPI) per PRU
    • 20-channel enhanced output (eGPO) per PRU
    • Embedded Peripherals and Memory
      • 1x UART, 1x ECAP
      • 1x MDIO, 1x IEP,
      • 1x 32KB Shared General Purpose RAM
      • 2x 8KB Shared Data RAM
      • 1x 12KB IRAM per PRU
      • ScratchPad (SPAD), MAC/CRC
    • Digital encoder and sigma-delta control loops
    • The PRU-ICSS enables advanced industrial protocols including:
      • EtherCAT, Ethernet/IP™,
      • PROFINET, IO-Link for order
    • Dedicated Interrupt Controller (INTC)
    • Dynamic CONTROLSS XBAR Integration

High-Speed Interfaces:

  • Integrated Ethernet switch supporting two external ports
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • 512x ALE engine-based Packet Classifiers
    • Priority flow control with up to 2KB packet size
    • Four CPU hardware interrupt pacing
    • IP/UDP/TCP checksum offload in hardware

Security:

  • Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITA
  • Secure boot support
    • Device Take Over Protection
    • Hardware-enforced root-of-trust
    • Authenticated boot
    • SW Anti-rollback protection
  • Debug security
    • Secure device debug only after proper authentication
    • Ability to disable device debug functionality
  • Device ID and Key Management
    • Support for OTP Memory (FUSEROM)
      • Store root keys & other security fields
    • Separate EFUSE controllers and FUSE ROMs
    • Unique Public Device Identifiers (UIDs)
  • Memory Protection Units (MPU)
    • Dedicated Arm® MPU per Cortex®-R5F core
    • System MPU - present at various interfaces in the SoC (MPU or Firewall)
    • 8-16 Programmable Regions
      • Enable/Privilege ID
      • Start/End Address
      • Read/Write/Cachable
      • Secure/Non-Secure
  • Cryptographic Acceleration
    • Cryptographic cores with DMA Support
    • AES - 128/192/256-bit key sizes
    • SHA2 - 256/384/512-bit support
    • DRBG with pseudo and true random number generator
    • PKA (public key accelerator) to assist in RSA/ECC processing

Functional Safety:

  • Enables design of systems with functional safety requirements
    • Error Signaling Module (ESM) with designated SAFETY_ERRORn pin
    • ECC or parity on calculation-critical memories
    • Built-In Self-Test (BIST) and fault-injection for CPU and on-chip RAM
    • Runtime internal diagnostic modules including voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engines for memory integrity checks
  • Functional Safety-Compliant targeted [Industrial]
    • Developed for functional safety applications
    • Documentation to be made available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL-3 targeted
    • Hardware integrity up to SIL-3 targeted
    • Safety-related certification
      • IEC 61508 planned
  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation to be made available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL-D targeted
    • Hardware integrity up to ASIL-D targeted
    • Safety-related certification
      • ISO 26262 planned

Technology / Package:

  • AEC-Q100 qualified for automotive applications
  • 45-nm technology
  • ZCZ Package
    • 324-pin NFBGA
    • 15.0 mm x 15.0 mm
    • 0.8 mm pitch

Processor Cores:

  • Single, dual, and quad-core Arm Cortex-R5F MCU with each core running up to 400 MHz
    • 16KB I-cache with 64-bit ECC per CPU core
    • 16KB D-cache with 32-bit ECC per CPU core
    • 64KB Tightly-Coupled Memory (TCM) with 32-bit ECC per CPU core
    • Lockstep or Dual-core capable clusters

Memory Subsystem:

  • 2MB of On-Chip RAM (OCSRAM)
    • 4 Banks x 512KB
    • ECC error protection
    • Internal DMA engine support

System on Chip (SoC) Services and Architecture:

  • 1x EDMA to support data movement functions
  • Device Boot supported from the following interfaces:
    • UART (Primary/Backup)
    • QSPI NOR Flash (4S/1S) (Primary)
  • Interprocessor communication modules
    • SPINLOCK module for synchronizing processes running on multiple cores
    • MAILBOX functionality implemented through CTRLMMR registers
  • Central Platform Time Sync (CPTS) support with time-sync and compare-event interrupt routers

Media and Data Storage:

  • 1x 4-bit Multi-Media Card/Secure Digital (MMC/SD) interface
  • General-Purpose Memory Controller (GPMC)
    • 16-bit parallel data bus with 22-bit address bus
    • Up to 4MB addressable memory space
    • Integrated Error Location Module (ELM) support for error checking

General Connectivity:

  • 6x Universal Asynchronous RX-TX (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 5x Local Interconnect Network (LIN) ports
  • 4x Inter-Integrated Circuit (I2C) ports
  • 4x Modular Controller Area Network (MCAN) modules with CAN-FD support
  • 1x Quad Serial Peripheral Interface (QSPI)
  • 4x Fast Serial Interface Transmitters (FSITX)
  • 4x Fast Serial Interface Receivers (FSIRX)
  • Up to 140 General-Purpose I/O (GPIO) pins

Sensing & Actuation:

  • Real-time Control Subsystem (CONTROLSS)
  • Flexible Input/Output Crossbars (XBAR)
  • 5x 12-bit Analog-to-Digital Converters (ADC)
    • 6-input SAR ADC up to 4 MSPS
      • 6x Single-ended channels OR
      • 3x Differential channels
    • Highly Configurable ADC Digital Logic
      • XBAR Start of Conversion Triggers (SOC)
      • User-defined Sample and Hold (S+H)
      • Flexible Post-Processing Blocks (PPB)
  • 10x Analog Comparators with Type-A programmable DAC reference (CMPSSA)
  • 10x Analog Comparators with Type-B programmable DAC reference (CMPSSB)
  • 1x 12-bit Digital-to-Analog Converter (DAC)
  • 32x Pulse Width Modulation (EPWM) modules
    • Single or Dual PWM channels
    • Advanced PWM Configurations
    • Extended HRPWM time resolution
  • 10x Enhanced Capture (ECAP) modules
  • 3x Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2x 4-Ch Sigma-Delta Filter Modules (SDFM)
  • Additional Signal-multiplex Crossbars (XBAR)

Industrial Connectivity:

  • Programmable Real-Time Unit (PRU-SS) and PRU-Industrial Communication Subsystem (PRU-ICSS)
    • Dual core Programmable Realtime Unit Subsystem (PRU0 / PRU1)
      • Deterministic Hardware
      • Dynamic Firmware
    • 20-channel enhanced input (eGPI) per PRU
    • 20-channel enhanced output (eGPO) per PRU
    • Embedded Peripherals and Memory
      • 1x UART, 1x ECAP
      • 1x MDIO, 1x IEP,
      • 1x 32KB Shared General Purpose RAM
      • 2x 8KB Shared Data RAM
      • 1x 12KB IRAM per PRU
      • ScratchPad (SPAD), MAC/CRC
    • Digital encoder and sigma-delta control loops
    • The PRU-ICSS enables advanced industrial protocols including:
      • EtherCAT, Ethernet/IP™,
      • PROFINET, IO-Link for order
    • Dedicated Interrupt Controller (INTC)
    • Dynamic CONTROLSS XBAR Integration

High-Speed Interfaces:

  • Integrated Ethernet switch supporting two external ports
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • 512x ALE engine-based Packet Classifiers
    • Priority flow control with up to 2KB packet size
    • Four CPU hardware interrupt pacing
    • IP/UDP/TCP checksum offload in hardware

Security:

  • Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITA
  • Secure boot support
    • Device Take Over Protection
    • Hardware-enforced root-of-trust
    • Authenticated boot
    • SW Anti-rollback protection
  • Debug security
    • Secure device debug only after proper authentication
    • Ability to disable device debug functionality
  • Device ID and Key Management
    • Support for OTP Memory (FUSEROM)
      • Store root keys & other security fields
    • Separate EFUSE controllers and FUSE ROMs
    • Unique Public Device Identifiers (UIDs)
  • Memory Protection Units (MPU)
    • Dedicated Arm® MPU per Cortex®-R5F core
    • System MPU - present at various interfaces in the SoC (MPU or Firewall)
    • 8-16 Programmable Regions
      • Enable/Privilege ID
      • Start/End Address
      • Read/Write/Cachable
      • Secure/Non-Secure
  • Cryptographic Acceleration
    • Cryptographic cores with DMA Support
    • AES - 128/192/256-bit key sizes
    • SHA2 - 256/384/512-bit support
    • DRBG with pseudo and true random number generator
    • PKA (public key accelerator) to assist in RSA/ECC processing

Functional Safety:

  • Enables design of systems with functional safety requirements
    • Error Signaling Module (ESM) with designated SAFETY_ERRORn pin
    • ECC or parity on calculation-critical memories
    • Built-In Self-Test (BIST) and fault-injection for CPU and on-chip RAM
    • Runtime internal diagnostic modules including voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engines for memory integrity checks
  • Functional Safety-Compliant targeted [Industrial]
    • Developed for functional safety applications
    • Documentation to be made available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL-3 targeted
    • Hardware integrity up to SIL-3 targeted
    • Safety-related certification
      • IEC 61508 planned
  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation to be made available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL-D targeted
    • Hardware integrity up to ASIL-D targeted
    • Safety-related certification
      • ISO 26262 planned

Technology / Package:

  • AEC-Q100 qualified for automotive applications
  • 45-nm technology
  • ZCZ Package
    • 324-pin NFBGA
    • 15.0 mm x 15.0 mm
    • 0.8 mm pitch

The AM263x Sitara™ Arm® Microcontrollers are built to meet the complex real-time processing needs of next generation industrial and automotive embedded products. The AM263x MCU family consists of multiple pin-to-pin compatible devices with up to four 400 MHz Arm® Cortex®-R5F cores. As an option, the Arm® R5F subsystem can be programmed to run in lockstep or dual-core mode for a multiple functional safety configurations. The industrial communications subsystem (PRU-ICSS) enables integrated industrial Ethernet communication protocols such as PROFINET®, TSN, Ethernet/IP®, EtherCAT® (among many others), standard Ethernet connectivity, and even custom I/O interfaces. The family is designed for the future of motor control and digital power applications with advanced analog sensing and digital actuation modules.

The multiple R5F cores are arranged in cluster subsystems with 256KB of shared tightly coupled memory (TCM) along with 2MB of shared SRAM, greatly reducing the need for external memory. Extensive ECC is included for on-chip memories, peripherals, and interconnects for enhanced reliability. Granular firewalls managed by the Hardware Security Manager (HSM) enable developers to implement stringent security-minded system design requirements. Cryptographic acceleration and secure boot are also available on AM263x devices.

TI provides a complete set of microcontroller software and development tools for the AM263x family of microcontrollers.

The AM263x Sitara™ Arm® Microcontrollers are built to meet the complex real-time processing needs of next generation industrial and automotive embedded products. The AM263x MCU family consists of multiple pin-to-pin compatible devices with up to four 400 MHz Arm® Cortex®-R5F cores. As an option, the Arm® R5F subsystem can be programmed to run in lockstep or dual-core mode for a multiple functional safety configurations. The industrial communications subsystem (PRU-ICSS) enables integrated industrial Ethernet communication protocols such as PROFINET®, TSN, Ethernet/IP®, EtherCAT® (among many others), standard Ethernet connectivity, and even custom I/O interfaces. The family is designed for the future of motor control and digital power applications with advanced analog sensing and digital actuation modules.

The multiple R5F cores are arranged in cluster subsystems with 256KB of shared tightly coupled memory (TCM) along with 2MB of shared SRAM, greatly reducing the need for external memory. Extensive ECC is included for on-chip memories, peripherals, and interconnects for enhanced reliability. Granular firewalls managed by the Hardware Security Manager (HSM) enable developers to implement stringent security-minded system design requirements. Cryptographic acceleration and secure boot are also available on AM263x devices.

TI provides a complete set of microcontroller software and development tools for the AM263x family of microcontrollers.

Download

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Technical documentation

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Type Title Date
* Data sheet AM263x Sitara™ Microcontrollers datasheet (Rev. C) PDF | HTML 18 Nov 2022
* Errata AM263x Sitara™ Microcontroller Silicon Revision 1.0A, 1.1A (Rev. B) PDF | HTML 06 Oct 2022
* User guide AM263x Sitara™ Microcontroller Technical Reference Manual (Rev. C) 01 Dec 2022
Application note DCC Computation Tool PDF | HTML 03 Feb 2023
User guide AM263x Sitara Control Card Hardware User's Guide (Rev. B) PDF | HTML 04 Jan 2023
User guide AM263x Sitara Processors Technical Reference Manual Register Addendum (Rev. C) 14 Dec 2022
Application note Debugging Sitara AM2x Microcontrollers PDF | HTML 24 Oct 2022
Application note AM263x Power Estimation Tool PDF | HTML 20 Oct 2022
Application note AM263x SW Build Sheet 17 Oct 2022
White paper 具備最佳性能的 EV 牽引逆變器設計優先順序 PDF | HTML 27 Sep 2022
White paper 최적의성능을 갖춘 EV 트랙션 인버터에서 설계 우선 순위 PDF | HTML 27 Sep 2022
White paper Design Priorities in EV Traction Inverter With Optimum Performance PDF | HTML 23 Sep 2022
Application note AM263x Hardware Design Guide PDF | HTML 20 Sep 2022
White paper Traction Inverters – A Driving Force Behind Vehicle Electrification PDF | HTML 08 Sep 2022
White paper 牽引逆變器 – 車輛電氣化背後的驅動力量 PDF | HTML 17 Aug 2022
White paper 트랙션 인버터 – 차량 전기화를 이끄는 동력 PDF | HTML 17 Aug 2022
Application note Optimized Trigonometric Functions on TI Arm Cores (Rev. A) PDF | HTML 08 Aug 2022
Application note AM263x QSPI Flash Selection Guide 28 Jul 2022
Application note AM263x Benchmarks PDF | HTML 09 May 2022
Technical article What is “real-time control” and why do you need it? 06 Apr 2022
Technical article How MCUs can unlock the full potential of electrification designs 21 Mar 2022
Application note AM263x for Traction Inverters PDF | HTML 21 Mar 2022
Technical article 5 ways high-performance MCUs are reshaping the industry 12 Jul 2021

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LP-AM263 — AM263x Arm®-based MCU general-purpose LaunchPad™ development kit

LP-AM263 is a cost-optimized development board for Sitara™ high-performance microcontrollers (MCUs) from the AM263x series. This board is ideal for initial evaluation and prototyping as it provides a standardized and easy-to-use platform to develop your next application.

LP-AM263 is equipped with a (...)

User guide: PDF | HTML
Not available on TI.com
Evaluation board

TMDSCNCD263 — AM263x Arm®-based MCU general-purpose controlCARD development kit

TMDSCNCD263 is an HSEC180 controlCARD based evaluation and development tool for the AM263x series Sitara™ high-performance microcontrollers. This board is ideal for initial evaluation and prototyping as it provides a standardized and easy-to-use platform to develop your next application. (...)

User guide: PDF | HTML
Not available on TI.com
Daughter card

TMDSHSECDOCK — HSEC180 controlCARD baseboard docking station

TMDSHSECDOCK is a baseboard that provides header-pin access to key signals on compatible HSEC180-based controlCARDs. A breadboard area is available for rapid prototyping. Board power can be provided by USB cable or a 5-V barrel supply.

User guide: PDF | HTML
Not available on TI.com
Software development kit (SDK)

MCU-PLUS-SDK-AM263X

AM263x software development kit (SDK) for Sitara™ microcontrollers

The AM263x microcontroller (MCU) plus software development kit (SDK) is a unified software platform for embedded processors providing easy setup and fast out-of-the-box access to examples, benchmarks and demonstrations. This software accelerates application development schedules by eliminating (...)
IDE, configuration, compiler or debugger

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)
IDE, configuration, compiler or debugger

SYSCONFIG — System configuration tool

To help simplify configuration challenges and accelerate software development, we created SysConfig, an intuitive and comprehensive collection of graphical utilities for configuring pins, peripherals, radios, subsystems, and other components.  SysConfig helps you manage, expose and resolve (...)
Simulation model

AM263x Sitara™ BSDL Model

SPRM772.ZIP (4 KB) - BSDL Model
Simulation model

AM263x Sitara™ IBIS Model

SPRM771.ZIP (2062 KB) - IBIS Model
Simulation model

AM263x Sitara™ Processors Thermal Model

SPRM769.ZIP (6 KB) - Thermal Model
Design tool

PROCESSORS-3P-SEARCH — Arm®-based MPU, Arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
Package Pins Download
NFBGA (ZCZ) 324 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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