SPRAD50A August   2022  – March 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Acronyms Used in This Document
  4. 2ROM Boot Requirements
  5. 3Application Requirements
  6. 4Additional Usage Factors
  7. 5Flash Support in MCU PLUS SDK
  8. 6Compatible Flash Devices
  9. 7References
  10. 8Revision History

2 ROM Boot Requirements

As seen in Figure 1-2, the boot flow process is a sequence adopted by AM263x that starts upon power-on. ROM code is already set to work in a certain way and expects specific instructions from the flash and expect specific timing and framing configurations for establishing communication. For the AM263x device, ROM code expects the following support:

  • Flash device must operate in the 3.3 V vicinity (typical range 2.3 V to 3.6 V)
  • Flash must be able to support Quad Output Fast Read (opcode 0x6B)
  • Flash must be able to support Fast Read in Single Mode (opcode 0x0B)
  • Device must allow 8 “dummy” clock cycles for setting up the initial address during the previously mentioned read operations
  • Flash must support 3-byte (24-bit) addressing mode by default
  • Flash memory size 4MB is recommended as a minimum

All of this information is available in the data sheet of the flash device being evaluated. A flash device must support all of the points mentioned above to meet AM263x compatibility requirements.