SPRAD66A February 2023 – December 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1
All address/control signals must be routed from the DDR controller to the LPDDR4 memory as described in the diagrams in Section 2.3. Address/control signals cannot be swapped with other signals. Data bit (DQx) swapping within a byte (for example, swapping D2 with D3) is allowed, but data bit DQx swapping across bytes (for example, swapping D4 and D13) is not allowed. When swapping bytes, all of the associated signals of the byte (DQx, DQSx, and DM) must be swapped together. In addition, byte lanes within a channel (for example, swapping byte 0 and 1) is allowed, but swapping byte lanes across channels (for example, swapping bytes 0 and 3) is not allowed. Byte lanes 0 and 1 must be routed to channel A of the LPDDR4 memory, and byte lanes 2 and 3 must be routed to channel B of the LPDDR4 memory. Use the DDR Subsystem Register Configuration Tool in SysConfig (https://dev.ti.com/sysconfig) to describe how the bits are swapped.