SPRAD66A February   2023  – December 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Ax/AM62Px LPDDR4 Board Design and Layout Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK and ADDR_CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK0 and ADDR_CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
    16. 2.16 Data Bus Inversion
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 System Level Simulation
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Eye Quality
        2. 3.5.3.2 Delay Report
        3. 3.5.3.3 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Appendix: SOC Package Delays
  8. 5References
  9. 6Revision History

3.6.1 Stack-Up

These guidelines recommend a 10- or 12-layer PCB stack-up for full device entitlement. Below are 10- and 12-layer example stack-ups:

  • Designs using FR4 products like 370HR are supported, but also recommend higher speed materials like ISOLA I-Speed (or equivalent) for increased margin. IT180A is also another material to help with cost vs. performance tradeoffs
  • This example routes data groups on layers 2 and 4. While this minimizes the via travel and therefore reduces via-to-via coupling, but it leaves a longer via stub, which might require back-drill.
  • In the 10-layer example, dynamic CA signals are routed on layer 7, and more static control signals routed on layer 9.
Table 3-4 Example 10-layer PCB Stackup for LPDDR4 (J7 EVM)
Layer No Stackup Routing Plan Highest Priorities and Layer
Solder mask
1 TOP - PWR/SIG BGA breakouts/VDD_CPU, VDD_CORE and VDD_DDR_1V1
2 PWR/SIG VDD_CPU and CORE/LPDDR (DBG #3/#1, CAT-Branches)
3 GND REF
4 PWR/SIG VDDA_PHYCORE_0V8, VDD_xxx, 0V85/LPDDR (DBG #2/#0)
5 PWR/GND VDDA_0V8_xxx and GND flood for LPDDR4
6 PWR/GND VDD_xxx, VDDA_xxx supplies and GND flooded for LPDDR4
7 SIG/PWR VDD_xxx, VDDA_xxx/LPDDR (Dynamic CA, Trunks)/SERDES
8 GND REF
9 SIG/PWR VDD_xxx, VDDA_xxx/LPDDR (static CA)
10 BOTTOM - SIG/PWR BGA breakouts/Pwr and GND plan segments
Solder mask
Table 3-5 Example 12-layer PCB Stackup for LPDDR4 (AM62Ax LP SK EVM)
Layer No Stackup Routing Plan Highest Priorities and Layer
Solder mask
1 TOP - PWR/SIG BGA breakouts, VDD_LPDDR4, GND
2 GND REF
3 PWR/SIG VDDA_1V8, GND, LPDDR (DBG #3/#1, CA T-Branches), LVCMOS escape
4 GND REF
5 SIG/GND GND, LPDDR (DBG #2/#0), LVCMOS escape
6 PWR/GND GND (under LPDDR), VDD_CORE, VDDR_CORE, VDDA_1V8, VDDSHVx
7 PWR DVDD_3V3, DVDD_1V8, VDD1_LPDDR4_1V8
8 PWR VDD_CORE, VDD_LPDDR4, VDDA_x
9 GND REF
10 SIG/GND GND, LPDDR (CA point-to-point, CA Trunks), LVCMOS escape
11 GND REF
12 BOTTOM - SIG/PWR GND, decaps, LVCMOS escape
Solder mask
Table 3-6 Example 12-layer PCB Stackup for LPDDR4 (AM62Px SK EVM)
Layer No Stackup Routing Plan Highest Priorities and Layer
Solder mask
1 TOP - PWR/SIG BGA breakouts, VDD_LPDDR4, GND
2 GND REF
3 PWR/SIG VDDA_1V8, GND, LPDDR (DBG #3/#1, CA T-Branches), LVCMOS escape
4 GND REF
5 SIG/GND GND, LPDDR (DBG #2/#0), LVCMOS escape
6 GND REF
7 PWR VDD_CORE, VDD_LPDDR4, DVDD_3V3
8 PWR/GND VDD1_LPDDR4_1V8, GND, VDDA_x
9 PWR/GND GND, VDDR_CORE, VDDA_1V8, DVDD_3V3, DVDD_1V8
10 SIG/GND GND, LPDDR (CA point-to-point, CA Trunks), LVCMOS escape
11 GND REF
12 BOTTOM - SIG/PWR GND, decaps, LVCMOS escape
Solder mask

Table 3-7 provides simulation results performed on sample designs, showing the impact of the PCB stackup (material, drill plan, and so forth) on LPDDR4 performance. The results showed that maximum bandwidth could be achieved on a FR4 solution, but required back-drilling. The higher frequency material could achieve same performance without back drill. Note the 8 layer design only achieved 3733, but this was due to other design compromises due to limited layers (solid reference planes, and so forth).

Table 3-7 Example LPDDR4 Performance Impact From J7 EVM Stackup
Design Material Layer Count Via Back Drilling Maximum LPDDR4 Speed (Mbps) (1)
J7 EVM I-Speed 16 Yes 4266
Ref Board I-Speed 10 No 4266
Ref Board 370HR 10 Yes 4266
Ref Board 370HR 8 No 3733
(1) These results are for J7 designs. For maximum supported data rates, see the device-specific data sheet.