SPRADL7 July   2025 F28E120SC

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Key Differences Between EPWM and MCPWM
  6. 3 Time-Base Submodule Differences
    1. 3.1 Register Differences
    2. 3.2 Driverlib Differences
  7. 4 Counter-Compare Submodule Differences
    1. 4.1 Register Differences
    2. 4.2 Driverlib Differences
  8. 5 Action-Qualifier Submodule Differences
    1. 5.1 Register Differences
    2. 5.2 Driverlib Differences
  9. 6 Dead-Band Submodule Differences
    1. 6.1 Register Differences
    2. 6.2 Driverlib Differences
  10. 7 Trip-Zone Submodule Differences
    1. 7.1 Register Differences
    2. 7.2 Driverlib Differences
  11. 8 Event-Trigger Submodule Differences
    1. 8.1 Register Differences
    2. 8.2 Driverlib Differences
  12. 9 Global Load Differences
    1. 9.1 Register Differences
    2. 9.2 Driverlib Differences
  13. 10Summary
  14. 11References

4.1 Register Differences

The register differences between EPWM and MCPWM for the Counter-Compare Submodule are listed in .

Table 4-1 Counter-Compare Submodule Register Differences Between EPWM and MCPWM

EPWM

MCPWM

Description

-

CMPCS.CMPCS

Addition of memory-mapped shadow register for CMPC

-

CMPDS.CMPDS

Addition of memory-mapped shadow register for CMPD

CMPA.CMPA

PWMx_CMPA.PWMx_CMPA

Separate CMPA registers for each PWM pair

CMPA.CMPA

PWMx_CMPAS.PWMx_CMPAS

Addition of memory-mapped shadow registers for CMPA

CMPB.CMPB

PWMx_CMPB.PWMx_CMPB

Separate CMPB registers for each PWM pair

CMPB.CMPB

PWMx_CMPBS.PWMx_CMPBS

Addition of memory-mapped shadow registers for CMPB

CMPCTL.LOADAMODE

CMPCTL.PWMx_LOADAMODE

Separate shadow load bits for CMPA for each PWM pair

CMPCTL.LOADBMODE

CMPCTL.PWMx_LOADBMODE

Separate shadow load bits for CMPB for each PWM pair

CMPCTL2.LOADCMODE

CMPCTL.LOADCMODE

Shadow load configuration of CMPD moved from CMPCTL2 to CMPCTL

CMPCTL2.LOADDMODE

CMPCTL.LOADDMODE

Shadow load configuration of CMPC moved from CMPCTL2 to CMPCTL

CMPCTL.LOADBSYNC

-

Loading CMPx registers on SYNCIN pulse removed from MCPWM

CMPCTL.SHDWAFULL

-

Replaced by memory-mapped shadow registers for CMPA

CMPCTL.SHDWAMODE

-

Shadow or active mode not selectable on MCPWM; only shadow load event needs to be configured and correct active or shadow register written to.

Note: Writing to the active register on MCPWM takes no effect unless freeze loading is selected in CMPCTL.LOADxMODE

CMPCTL.SHDWBFULL

-

Replaced by memory-mapped shadow registers for CMPA

CMPCTL.SHDWBMODE

-

Shadow or active mode not selectable on MCPWM; only shadow load event needs to be configured and correct active or shadow register be written to.

Note: Writing to the active register on MCPWM takes no effect unless freeze loading is selected in CMPCTL.LOADxMODE

CMPCTL2.LOADCSYNC

-

Loading CMPx registers on SYNCIN pulse removed from MCPWM

CMPA.CMPAHR

-

HRPWM removed from MCPWM

CMPCTL.LOADASYNC

-

Loading CMPx registers on SYNCIN pulse removed from MCPWM

CMPB.CMPBHR

-

HRPWM removed from MCPWM

CMPCTL2.LOADDSYNC

-

Loading CMPx registers on SYNCIN pulse removed from MCPWM

CMPCTL2.SHDWCMODE

-

Shadow or active mode not selectable on MCPWM; only shadow load event needs to be configured and correct active or shadow register written to.

Note: Writing to the active register on MCPWM takes no effect unless freeze loading is selected in CMPCTL.LOADxMODE

CMPCTL2.SHDWDMODE

-

Shadow or active mode not selectable on MCPWM; only shadow load event needs to be configured and correct active or shadow register written to.

Note: Writing to the active register on MCPWM takes no effect unless freeze loading is selected in CMPCTL.LOADxMODE