SPRADT0 February   2025 TMS320F280049C , TMS320F280049C-Q1

 

  1.   1
  2.   Abstract
  3. 1Basic Principles of SAR ADCs
  4. 2Causes of ADC Crosstalk
  5. 3Calculation of ADC Sample-and-Hold Time
  6. 4ADC External Circuit Parameter Design and Experiments
    1. 4.1 Design of an Amplifier-Based RC Filter Circuit:
    2. 4.2 Designing a Sufficiently Large Cs Capacitor for Amplifier-Free Circuits
  7. 5Summary
  8. 6References

3 Calculation of ADC Sample-and-Hold Time

Internal ADC Circuit ModelFigure 3-1 Internal ADC Circuit Model

Figure 3-1 shows a simplified model of the ADC internal circuit. Here, Rs and Cs are the external RC filter circuit components; Ron and CH are the internal RC circuit components of the ADC; N is the ADC resolution in bits; and Cp is the parasitic input capacitance. In general, Cp is much smaller than the external filter capacitor Cs and can therefore be neglected in calculations.

The RC time constant of the entire circuit is:

Equation 1. τ = ( R o n + R s ) * C H + R s * ( C S + C P )

The number of time constants required to achieve an error of 1/2 LSB is:

Equation 2. K = ln ⁡ ( 2 N + 1 ) - ln ⁡ ( C S + C P C H )

The required sample-and-hold time is:

T=K∗τ

In other words, to achieve a sampling accuracy of 1/2 LSB, at least K∗τ time is required.

From the above equations, it can be seen that the parameters with the greatest influence on the required sample-and-hold time T are the filter capacitor Cs and resistor Rs. The other parameters, Ron, Cp, and CH, are fixed. The relationship between Rs and T is essentially linear, whereas the relationship between Cs and T is not linear.

For example, for the ADC of the F280049, when using the internal reference voltage, the datasheet provides CH = 7.5pF, Ron = 860Ω, Cp = 13.7pF, and N = 12.

F280049 ADC Internal Circuit ParametersFigure 3-2 F280049 ADC Internal Circuit Parameters

Based on different values of Rs and Cs, the required sample-and-hold time T can be calculated.

The following are calculation results for different Rs and Cs values:

Parameter Example 1 Example 2 Example 3 Example 4 Example 5 Example 6
Cs 820pf 10nf 100nf 10nf 1nf 100nf
Rs 100ohm 100ohm 100ohm 10Kohm 10Kohm 10Kohm
CH 7.5pf 7.5pf 7.5pf 7.5pf 7.5pf 7.5pf
Cp 13.7pf 13.7pf 13.7pf 13.7pf 13.7pf 13.7pf
Ron 860ohm 860ohm 860ohm 860ohm 860ohm 860ohm
Settling error 0.5LSB 0.5LSB 0.5LSB 0.5LSB 0.5LSB 0.5LSB
t 87.9ns 1.0us 10.0us 100.2us 10.2us 1.0ms
k 4.3 1.8 -4.9 1.8 4.1 -0.49
Settling time T 377.8ns 1.82us -4.9us 181.8us 41.9us -487.3us
ACQPS 38 182 7 18179 4192 7

ACQPS is equal to the number of MCU system clock cycles (SYSCLK) corresponding to the sample-and-hold time minus 1. The relationship is:

ACQPS = T / SYSCLK - 1.

ACQPS is configurable in software. For the F280049, the configuration range is 7 to 512.

The calculations above show that when Rs is fixed and Cs increases from approximately 1nf to 100nf, the sample-and-hold time first increases and then decreases, even becoming negative. A negative time indicates that the minimum sample-and-hold time is sufficient to meet the accuracy requirement, meaning ACQPS can simply be set to 7.

The sample-and-hold times calculated in Example 4 and 5 greatly exceed 512 system clock cycles, indicating that the maximum configurable ADC sample-and-hold time is insufficient, resulting in some sacrifice of sampling accuracy.

Figure 3-3 more intuitively shows the relationship between sample-and-hold time and Cs. When Rs is fixed at 100Ω and Cs varies from 1pf to 100nF, the required sample-and-hold time to achieve an error within 0.5LSB changes as follows.

Relationship Between Sample-and-Hold Time T and Cs CapacitanceFigure 3-3 Relationship Between Sample-and-Hold Time T and Cs Capacitance

Initially, as Cs increases, the required sample-and-hold time T also increases. However, once Cs becomes relatively large, such as tens of nF, T decreases rapidly. Therefore, the filter capacitor Cs is generally designed to be either relatively large or relatively small, allowing short sample-and-hold times while maintaining sufficient sampling accuracy and avoiding the effects of crosstalk.