SPRADU0 August   2026 TMS320F28P650DK

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2BBU Interleave DC/DC Topology and Control Framework
  6. 3F28P65X Real-Time Control Signal Path
  7. 4F28P65X Hardware SysConfig Configuration and Project Implementation
    1. 4.1 CMPSS Configuration Considerations
      1. 4.1.1 CMPSS Ramp Compensation and Cycle-by-Cycle Current Limiting
      2. 4.1.2 Application of CMPSS Negative Current Shutdown
      3. 4.1.3 CMPSS Fault Protection
    2. 4.2 EPWM XBAR Configuration
    3. 4.3 EPWM Configuration
      1. 4.3.1 Interleaved PWM Global Configuration
      2. 4.3.2 Single-Phase EPWM Module Configuration
  8. 5F28P65x Dual-CPU Co-Working and Considerations
  9. 6Test Waveforms
  10. 7References

1 Introduction

The BBU (Battery Backup Unit) in data centers needs to quickly take over load power supply within 2~5 minutes after AC/PSU power outage to buy time windows for bus switching, load migration, and safe shutdown. As the sole power interface between the battery and the data center bus, the dynamic response capability of the DC/DC converter directly determines the availability of the BBU.

Traditional analog control schemes (such as peak current mode PWM controllers) lack flexibility in the face of requirements like multiphase paralleling, online parameter adjustment, and firmware upgrades. The F28P65x series DSP, due to its rich integrated peripherals, efficient loop control, and dual-CPU multi-Flash Bank features, can overcome the challenges of high power density, dynamic response, and non-disruptive online upgrades in BBU applications. Taking an asymmetric interleaved scheme with multiphase discharge Boost and charge Buck as an example, this paper introduces the hardware signal chain design, software configuration methods, and key points of dual-CPU co-working for F28P65x to achieve peak current mode control.