SPRADU0 August   2026 TMS320F28P650DK

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2BBU Interleave DC/DC Topology and Control Framework
  6. 3F28P65X Real-Time Control Signal Path
  7. 4F28P65X Hardware SysConfig Configuration and Project Implementation
    1. 4.1 CMPSS Configuration Considerations
      1. 4.1.1 CMPSS Ramp Compensation and Cycle-by-Cycle Current Limiting
      2. 4.1.2 Application of CMPSS Negative Current Shutdown
      3. 4.1.3 CMPSS Fault Protection
    2. 4.2 EPWM XBAR Configuration
    3. 4.3 EPWM Configuration
      1. 4.3.1 Interleaved PWM Global Configuration
      2. 4.3.2 Single-Phase EPWM Module Configuration
  8. 5F28P65x Dual-CPU Co-Working and Considerations
  9. 6Test Waveforms
  10. 7References

2 BBU Interleave DC/DC Topology and Control Framework

Interleaved BOOST TopologyFigure 2-1 Interleaved BOOST Topology

BBU/CBU requires extremely high power density. Non-isolated interleaved Buck/Boost is widely used due to its advantages of small magnetic component volume and ripple cancellation to reduce output capacitance. Data centers generally do not require fast charging for BBU, but require it to provide massive emergency peak power within a short period (typically 2-5 minutes); therefore, the number of charging phases is generally smaller than that of discharging phases. As shown in Figure 2-1, since the charging Buck is easy to implement, this system takes the multiphase interleaved discharge Boost as an example for introduction. In certain scenarios with higher power density requirements, bidirectional Buck/Boost topology is also selected, but it also brings challenges in redundancy design and charge/discharge timing control.

The control challenges lie in the dynamic performance requirements during load empty-to-full switching and phase-to-phase current sharing. Peak current mode (PCM) control is generally used in design. Through the inner current loop, the inductor acts as a controlled current source, reducing the small-signal transfer function of the traditional Boost to a first-order single-pole system, avoiding the risk of phase deterioration caused by the right half-plane zero (RHPZ), and allowing the control bandwidth of the outer voltage loop to be significantly widened to enhance system dynamic performance. Phase-to-phase current sharing adopts an adaptive scheme sharing COMP, where PWM comparators across phases uniformly use the same voltage error signal as input to compare with peak current signals before triggering duty cycles. When an inductor inductance in a certain phase is smaller and causes a faster current rising slope, the phase current will trigger the comparator flip earlier at the same threshold, thereby producing a narrower duty cycle within that cycle and automatically suppressing average energy output. The entire current sharing process is completed at the cycle-by-cycle hardware level without occupying ADC sampling channels or main control processing resources. Compared with droop methods and democratic current sharing methods, it offers significant advantages in integration.