In the multiphase Boost discharge circuit, we allocate a CMPSS comparison module to each Boost output phase to trigger the capture of CBC events under peak control mode. Because the input end of the BBU is a battery, it has a wide input voltage range and operates in Continuous Conduction Mode (CCM). Duty cycles exceeding 50% are common, and this operating condition can cause sub-harmonic oscillation in the inner current loop due to error non-convergence. Therefore, the design of ramp compensation is particularly important.

The CMPSS module operates in count-down mode, setting the corresponding Ramp Generator Step Value and Ramp Clock Frequency according to the falling slope of the inductor current. The synchronization source of the ramp generator is then configured as the corresponding EPWM module, so that the ramp generator resets its value to the preset maximum at the start of the EPWM period.

Cycle-by-cycle current limiting protection (CBC) is generally used to protect the inductor peak current within a switching period, usually implemented by external analog circuits or additional comparator circuits. CMPSS offers another possibility: by limiting the Max Ramp Generator Reference Value to the maximum allowable inductor current, CBC can be conveniently achieved through a single CMPSS without any extra external circuits, making it suitable for applications with high power density requirements such as BBUs. However, the following points also need to be noted:

1. Because there is a certain delay from CMPSS to the final PWM (typically around 50ns), design redundancy for inductors and power devices must be fully considered.
2. The setting of the maximum initial value should be fully considered during design, as RAMP decreases with continuous turn-on of the duty cycle, resulting in single-cycle energy output limitation.

Based on the above explanations, the specific configuration process of CMPSS is as follows:

1. The ramp generator configuration is as follows, with the maximum reference value range being 0-65535. Based on the step value and clock frequency, the reference voltage at maximum period can be calculated. It should be noted here that the reset time of the maximum reference value is bound to the EPWM module:
   
2. The CMPSS positive input pin configuration is as follows; each CMPSS has up to four selectable input pins.
   
3. DAC-related configurations are set as follows.