The block diagram of the PRU (Programmable Real‑Time Unit) on TI SoCs is shown in Figure 1-1. The PRU is a RISC core specifically designed for hard real‑time, low‑latency control. It guarantees deterministic timing at the physical boundary through its pipeline‑free single‑cycle execution mechanism and direct pin‑mapping architecture.

In actual industrial applications, systems often need to interface with external devices that do not use standard protocols. For interfaces with special timing requirements that the SoC may not be able to connect to directly, the traditional approach is to use an FPGA to achieve high‑bandwidth communication between the SoC and the special‑timing peripheral. However, because Sitara processors include a PRU (programmable real-time unit) core internally, there is no need to add an FPGA, ASIC, CPLD, or similar device in such cases. Another approach is to use an MCU's GPIO pins for simulation; however, using an MCU core to toggle GPIO pins has fundamental drawbacks. Compared to an FPGA, a standard MCU exhibits higher latency and lower determinism when interacting with GPIOs. When software is used to control GPIO toggling, the achievable frequency and precision are severely limited by internal bus latency, making it impossible to meet the requirements for duty‑cycle control and precise timing control.

The PRU system contains 32 32‑bit registers, two of which are dedicated to GPIO functions. One register is directly connected to the General‑Purpose Output (GPO) signals; writing to this register toggles the GPO signals. The other register is directly connected to the General‑Purpose Input (GPI) signals; reading this register reads the GPI signals. With this design, there is a direct connection from the PRU to the actual GPIO pins, and the performance of both input and output signals is improved. The PRU has instructions that pause program execution until a GPI event occurs, enabling optimal‑latency output response upon detection of an input trigger. The PRU can thus achieve fully deterministic timing relationships between a single input and output, as well as among multiple input or multiple output signals. This highly deterministic physical‑layer communication is decoupled from the complex, non‑real‑time upper‑layer operating system. At a 333MHz core frequency, the single‑cycle GPIO execution precision is controlled to 3ns, and the interrupt‑response cycle can be controlled to 6ns. In addition, the PRU core integrates an innovative Broadside Interface, which breaks the traditional word‑by‑word read bottleneck of general‑purpose CPUs. This interface allows the PRU to achieve parallel bulk‑data throughput of up to 124 bytes with local hardware accelerators in a single clock cycle. Furthermore, each PRU core is equipped with 2kB of dedicated Broadside RAM. This memory is mounted to the same dedicated Broadside bus, providing access speeds equivalent to shared memory while also guaranteeing zero bus contention during multi‑core concurrency through physical isolation.

The above description applies to all Sitara processors with a PRU subsystem, including the AM243x, AM263x, AM335x, AM437x, AM57x, AM62x, AM64x, and AM65x. TI processors include various PRU subsystems such as PRU‑ICSS, PRU‑ICSSG, and PRUSS. This document focuses primarily on the PRUSS for the AM625 series. For specific differences among each PRU subsystem, please refer to the following document: PRU-ICSS Feature Comparison (Rev. H). The high‑speed UART implementation described in this document is based on PRUSS and can, in theory, be directly ported to other PRU subsystems.