Since the PRU internally integrates only one hardware high‑speed UART channel, when multiple high‑speed UARTs are required, we can use the PRU I/O's PEFIF (Peripheral Interface) mode for hardware‑assisted reception and transmission of UART data. The three‑channel peripheral interface present on each PRU is typically used to support serial‑based motor encoder protocols such as EnDat 2.2 and BiSS. Each transmit PERIF channel has a 32‑bit FIFO for directly storing transmit data, and each receive PERIF channel has a 4‑bit FIFO for receiving data. We can use this interface to send and receive data via the UART protocol.

The architecture of the low‑latency, multi‑channel high‑speed UART transmission system based on the PRU, i.e., the hardware implementation of the data‑link layer, is shown in Figure 3-1. By hardware‑accelerating traditional low‑speed/high‑latency tasks and using the PRU real‑time core for data scheduling, it achieves extremely high throughput and microsecond‑level ultra‑low deterministic latency.

The entire architecture is physically and logically divided into two core latency domains to isolate the uncertainty caused by system scheduling on the ARM side. The high‑latency domain primarily includes the ARM core (responsible for high‑level application logic), DMASS (DMA system), general‑purpose timers, standard UARTs (with 64‑byte TX‑FIFO), MSRAM, and DDR memory. Processing in the above components involves multiple layers of bus arbitration and general‑purpose OS scheduling, resulting in an overall access latency of approximately 250ns that varies with system load, with jitter potentially reaching several microseconds. The low‑latency domain mainly consists of the ICSS internal interconnect bus (32‑bit, 250MHz), PRU 0/PRU 1 dual cores, dedicated DMA (XFR2VBUS RD DMA), SPAD shared memory, and peripheral PERIF TX/RX hardware. Based on the 250MHz ICSS bus, it achieves a read latency of 9ns and a write latency of 6ns. Furthermore, to achieve smooth and efficient data transfers from the high‑latency storage area to the real‑time transmitter, the system employs a dedicated channel architecture with Ping‑Pong buffer channels. Four independent logical channels (Channel 1–4) are deployed in the low‑latency domain, each equipped with a double‑buffer structure (e.g., Channel 1 includes Tx1a and Tx1b for Ping‑Pong operation), with each individual buffer being 128 bytes in size. This design allows the DMA to transfer the current data block while the PRU simultaneously reads and transmits the other data block without contention. The ARM interacts with the PRU core via the INTC (Interrupt Controller). The ARM transfers and refreshes the data for these four channels via the Main CBASS. Refreshing 88 bytes of data each time takes approximately 70μs. Transmitting 128 bytes (1280 bits) at 12Mbps takes about 106.6μs. Therefore, the 70μs window is sufficient for UART transmit and receive requirements. The core computation and control of UART data are performed cooperatively by the two PRU cores running at 333MHz, with PRU 0 dedicated to UART data transmission for all four channels. The transmit data is directly fetched from the channel buffers on the PRU-ICSS interconnect bus through the dedicated XFR2VBUS RD DMA, without requiring intervention by the ARM core. PRU 1 is dedicated to UART data reception for the four channels, feeding received data back to the bus via the lower XFR2VBUS RD DMA.

Transmit data is ultimately serialized and output through hardware peripherals and pins, exhibiting extremely high determinism: the high‑speed hardware UART is directly integrated in the low‑latency domain, supports rates up to 12 Mbps, and includes a built‑in 16‑byte TX FIFO. The other three channels utilize the PRU-specific peripheral transmit and receive interfaces (3 PERIF TX/RX). The PRU core drives these PERIF TX and RX interfaces directly via the dedicated R30/R31 register interface with extremely low jitter, outputting to the physical pins. Even under high throughput, there is no long‑delay idle between serial frames. In this design, full‑speed 12Mbps data transmission is achieved. Through the SPAD (Scratchpad shared memory), PRU0 and PRU1 can exchange data directly at high speed with zero latency, which can be used directly for inter‑core synchronization of PRU cores.