As modern industry demands higher production precision and monitoring frequency, UART communication is evolving toward higher frequencies, greater throughput, and megabit‑per‑second (Mbps) data rates. This trend often requires continuous data streaming to the main control unit at rates of several megabits per second. Such high‑speed UART communication places higher demands on the real‑time response capability and throughput performance of the underlying control system. In existing industrial embedded designs, the mainstream approach typically uses a general‑purpose MPU (e.g., ARM Cortex‑A series) running a general‑purpose OS such as Linux, with the chip's built‑in hardware UART controller handling UART data. This traditional "ARM + Linux + hardware UART" architecture performs well at low baud rates; however, in high‑speed (Mbps‑level) scenarios, its task scheduler, virtual memory management, and complex network protocol stack introduce unpredictable latency jitter. When a high‑speed UART generates high‑frequency interrupts, the thread‑scheduling latency of the Linux OS typically ranges from tens to hundreds of microseconds. At Mbps‑level baud rates, the transmission time for a single byte is only a few microseconds or a few hundred nanoseconds. Although hardware UART chips incorporate 16‑byte or 64‑byte FIFOs (First‑In, First‑Out buffers), under high‑speed communication, these FIFOs can easily fill up within a few microseconds. If not serviced in time, this readily leads to overflow errors and packet loss. To prevent packet loss, the system is forced to expend a significant amount of computational power on serial UART processing.

TI processors support multiple UART interfaces for communication. Table 1-1 lists the number of UARTs supported by various TI processors and their maximum speeds. Taking AM62x as an example, the chip natively supports up to 9 UARTs. However, due to the limitations of traditional Linux and hardware UARTs, the maximum software‑supported UART speed on TI Sitara processors is 3Mbps. Even though UARTs of TI processor support DMA mode and other optimization measures to reduce CPU usage during reception and transmission, actual tests with the traditional approach still cannot achieve more than 3Mbps throughput without adversely affecting other system tasks (i.e., without significantly increasing CPU load). Therefore, this document proposes using the PRU to simulate a UART in order to achieve a higher speed (12Mbps) without substantially increasing CPU load.