SPRSP96B March   2024  – March 2026 TDA4AEN-Q1 , TDA4VEN-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      10
      2.      11
    3. 5.3 Signal Descriptions
      1.      13
      2. 5.3.1  CPSW3G
        1. 5.3.1.1 MAIN Domain
          1.        16
          2.        17
          3.        18
          4.        19
      3. 5.3.2  CPTS
        1. 5.3.2.1 MAIN Domain
          1.        22
      4. 5.3.3  CSI-2
        1. 5.3.3.1 MAIN Domain
          1.        25
          2.        26
          3.        27
          4.        28
      5. 5.3.4  DDRSS
        1. 5.3.4.1 MAIN Domain
          1.        31
      6. 5.3.5  DSI
        1. 5.3.5.1 MAIN Domain
          1.        34
      7. 5.3.6  DSS
        1. 5.3.6.1 MAIN Domain
          1.        37
      8. 5.3.7  ECAP
        1. 5.3.7.1 MAIN Domain
          1.        40
          2.        41
          3.        42
      9. 5.3.8  Emulation and Debug
        1. 5.3.8.1 MAIN Domain
          1.        45
        2. 5.3.8.2 MCU Domain
          1.        47
      10. 5.3.9  EPWM
        1. 5.3.9.1 MAIN Domain
          1.        50
          2.        51
          3.        52
          4.        53
      11. 5.3.10 EQEP
        1. 5.3.10.1 MAIN Domain
          1.        56
          2.        57
          3.        58
      12. 5.3.11 GPIO
        1. 5.3.11.1 MAIN Domain
          1.        61
          2.        62
        2. 5.3.11.2 MCU Domain
          1.        64
      13. 5.3.12 GPMC
        1. 5.3.12.1 MAIN Domain
          1.        67
      14. 5.3.13 I2C
        1. 5.3.13.1 MAIN Domain
          1.        70
          2.        71
          3.        72
          4.        73
          5.        74
        2. 5.3.13.2 MCU Domain
          1.        76
        3. 5.3.13.3 WKUP Domain
          1.        78
      15. 5.3.14 MCAN
        1. 5.3.14.1 MAIN Domain
          1.        81
          2.        82
        2. 5.3.14.2 MCU Domain
          1.        84
          2.        85
      16. 5.3.15 MCASP
        1. 5.3.15.1 MAIN Domain
          1.        88
          2.        89
          3.        90
          4.        91
          5.        92
      17. 5.3.16 MCSPI
        1. 5.3.16.1 MAIN Domain
          1.        95
          2.        96
          3.        97
        2. 5.3.16.2 MCU Domain
          1.        99
          2.        100
      18. 5.3.17 MDIO
        1. 5.3.17.1 MAIN Domain
          1.        103
      19. 5.3.18 MMC
        1. 5.3.18.1 MAIN Domain
          1.        106
          2.        107
          3.        108
      20. 5.3.19 OLDI
        1. 5.3.19.1 MAIN Domain
          1.        111
      21. 5.3.20 OSPI
        1. 5.3.20.1 MAIN Domain
          1.        114
      22. 5.3.21 Power Supply
        1.       116
      23. 5.3.22 Reserved
        1.       118
      24. 5.3.23 SERDES
        1. 5.3.23.1 MAIN Domain
          1.        121
          2.        122
          3.        123
      25. 5.3.24 System and Miscellaneous
        1. 5.3.24.1 Boot Mode Configuration
          1. 5.3.24.1.1 MAIN Domain
            1.         127
        2. 5.3.24.2 Clock
          1. 5.3.24.2.1 MCU Domain
            1.         130
          2. 5.3.24.2.2 WKUP Domain
            1.         132
        3. 5.3.24.3 System
          1. 5.3.24.3.1 MAIN Domain
            1.         135
          2. 5.3.24.3.2 MCU Domain
            1.         137
          3. 5.3.24.3.3 WKUP Domain
            1.         139
        4. 5.3.24.4 VMON
          1.        141
      26. 5.3.25 TIMER
        1. 5.3.25.1 MAIN Domain
          1.        144
        2. 5.3.25.2 MCU Domain
          1.        146
        3. 5.3.25.3 WKUP Domain
          1.        148
      27. 5.3.26 UART
        1. 5.3.26.1 MAIN Domain
          1.        151
          2.        152
          3.        153
          4.        154
          5.        155
          6.        156
          7.        157
        2. 5.3.26.2 MCU Domain
          1.        159
        3. 5.3.26.3 WKUP Domain
          1.        161
      28. 5.3.27 USB
        1. 5.3.27.1 MAIN Domain
          1.        164
          2.        165
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings for AEC - Q100 Qualified Devices in the AMW Package
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Power Consumption Summary
    7. 6.7  Electrical Characteristics
      1. 6.7.1  I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.7.2  Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.7.3  High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.7.4  Low-Frequency Oscillator (LFXOSC) Electrical Characteristics
      5. 6.7.5  eMMCPHY Electrical Characteristics
      6. 6.7.6  SDIO Electrical Characteristics
      7. 6.7.7  LVCMOS Electrical Characteristics
      8. 6.7.8  OLDI LVDS (OLDI) Electrical Characteristics
      9. 6.7.9  CSI-2 (D-PHY) Electrical Characteristics
      10. 6.7.10 DSI (D-PHY) Electrical Characteristics
      11. 6.7.11 USB2PHY Electrical Characteristics
      12. 6.7.12 SerDes PHY Electrical Characteristics
      13. 6.7.13 DDR Electrical Characteristics
    8. 6.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.8.2 Hardware Requirements
      3. 6.8.3 Programming Sequence
      4. 6.8.4 Impact to Your Hardware Warranty
    9. 6.9  Thermal Resistance Characteristics
      1. 6.9.1 Thermal Resistance Characteristics for AMW Package
    10. 6.10 Temperature Sensor Characteristics
    11. 6.11 Timing and Switching Characteristics
      1. 6.11.1 Timing Parameters and Information
      2. 6.11.2 Power Supply Requirements
        1. 6.11.2.1 Power Supply Slew Rate Requirement
        2. 6.11.2.2 Power Supply Sequencing
          1. 6.11.2.2.1 Power-Up Sequencing
          2. 6.11.2.2.2 Power-Down Sequencing
          3. 6.11.2.2.3 Partial IO Power Sequencing
      3. 6.11.3 System Timing
        1. 6.11.3.1 Reset Timing
        2. 6.11.3.2 Error Signal Timing
        3. 6.11.3.3 Clock Timing
      4. 6.11.4 Clock Specifications
        1. 6.11.4.1 Input Clocks / Oscillators
          1. 6.11.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 6.11.4.1.1.1 Load Capacitance
            2. 6.11.4.1.1.2 Shunt Capacitance
          2. 6.11.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
          3. 6.11.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source
          4. 6.11.4.1.4 WKUP_LFOSC0 LVCMOS Digital Clock Source
          5. 6.11.4.1.5 WKUP_LFOSC0 Not Used
        2. 6.11.4.2 Output Clocks
        3. 6.11.4.3 PLLs
        4. 6.11.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.11.5 Peripherals
        1. 6.11.5.1  ATL
          1. 6.11.5.1.1 ATL_PCLK Timing Requirements
          2. 6.11.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.11.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.11.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.11.5.2  CPSW3G
          1. 6.11.5.2.1 CPSW3G MDIO Timing
          2. 6.11.5.2.2 CPSW3G RMII Timing
          3. 6.11.5.2.3 CPSW3G RGMII Timing
        3. 6.11.5.3  CPTS
        4. 6.11.5.4  CSI-2
        5. 6.11.5.5  CSI-2 TX
        6. 6.11.5.6  DDRSS
        7. 6.11.5.7  DSI
        8. 6.11.5.8  DSS
        9. 6.11.5.9  ECAP
        10. 6.11.5.10 Emulation and Debug
          1. 6.11.5.10.1 Trace
          2. 6.11.5.10.2 JTAG
        11. 6.11.5.11 EPWM
        12. 6.11.5.12 EQEP
        13. 6.11.5.13 GPIO
        14. 6.11.5.14 GPMC
          1. 6.11.5.14.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.11.5.14.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.11.5.14.3 GPMC and NAND Flash — Asynchronous Mode
        15. 6.11.5.15 I2C
        16. 6.11.5.16 MCAN
        17. 6.11.5.17 MCASP
        18. 6.11.5.18 MCSPI
          1. 6.11.5.18.1 MCSPI — Controller Mode
          2. 6.11.5.18.2 MCSPI — Peripheral Mode
        19. 6.11.5.19 MMCSD
          1. 6.11.5.19.1 MMC0 - eMMC Interface
            1. 6.11.5.19.1.1  Legacy SDR Mode
            2. 6.11.5.19.1.2  High Speed SDR Mode
            3. 6.11.5.19.1.3  High Speed DDR Mode
            4. 6.11.5.19.1.4  HS200 Mode
            5. 6.11.5.19.1.5  HS400 Mode
            6. 6.11.5.19.1.6  UHS–I SDR12 Mode
            7. 6.11.5.19.1.7  UHS–I SDR25 Mode
            8. 6.11.5.19.1.8  UHS–I SDR50 Mode
            9. 6.11.5.19.1.9  UHS–I DDR50 Mode
            10. 6.11.5.19.1.10 UHS–I SDR104 Mode
          2. 6.11.5.19.2 MMC1/MMC2 - SD/SDIO Interface
            1. 6.11.5.19.2.1 Default Speed Mode
            2. 6.11.5.19.2.2 High Speed Mode
            3. 6.11.5.19.2.3 UHS–I SDR12 Mode
            4. 6.11.5.19.2.4 UHS–I SDR25 Mode
            5. 6.11.5.19.2.5 UHS–I SDR50 Mode
            6. 6.11.5.19.2.6 UHS–I DDR50 Mode
            7. 6.11.5.19.2.7 UHS–I SDR104 Mode
        20. 6.11.5.20 OLDI
          1. 6.11.5.20.1 OLDI0 Switching Characteristics
        21. 6.11.5.21 OSPI
          1. 6.11.5.21.1 OSPI0 PHY Mode
            1. 6.11.5.21.1.1 OSPI0 With PHY Data Training
            2. 6.11.5.21.1.2 OSPI0 Without Data Training
              1. 6.11.5.21.1.2.1 OSPI0 PHY SDR Timing
              2. 6.11.5.21.1.2.2 OSPI0 PHY DDR Timing
          2. 6.11.5.21.2 OSPI0 Tap Mode
            1. 6.11.5.21.2.1 OSPI0 Tap SDR Timing
            2. 6.11.5.21.2.2 OSPI0 Tap DDR Timing
        22. 6.11.5.22 PCIe
        23. 6.11.5.23 Timers
        24. 6.11.5.24 UART
        25. 6.11.5.25 USB
  8. 7 Detailed Description
    1. 7.1 Overview
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Supply Designs
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 LPDDR4 Board Design and Layout Guidelines
      2. 8.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (only available in Octal SPI devices)
      3. 8.2.3 USB VBUS Design Guidelines
      4. 8.2.4 System Power Supply Monitor Design Guidelines
      5. 8.2.5 High Speed Differential Signal Routing Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

6.5 Operating Performance Points

Table 6-1 defines the maximum operating frequency of the clocks for each device speed grade and Table 6-2 defines the only valid Operating Performance Points (OPPs) for the device subsystem and core clocks.

Table 6-1 Device Speed Grades
Speed
Grade		 VDD_CORE
(V)(1)		 MAXIMUM OPERATING FREQUNCY (MHz) MAXIMUM DATA RATE (MT/s)(2)
A53SS
(Cortex-A53x)		 C7/MMA R5FSS0 MAIN DOMAIN SYSCLK MCU R5F MCU DOMAIN SYSCLK DEVICE MGR R5F DEVICE MGR DOMAIN CLK HSM GPU VPAC DMPAC VPU LPDDR4
J 0.75 1250 1000(3) 800 500 800 400 800 400 400 720 600 428.5 500 3200 to 3733
K 0.85 1400 1000 800 3466 to 4000
(1) Nominal operating voltage, see Section 6.4.
(2) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation. Refer to LPDDR4 Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency. It is recommended that software uses the minimum required LPDDR4 transfer rate that satisfies the performance requirements of the system.
(3) The C7/MMA speed grade is increased from 912.5MHz to 1000MHz for all material with LTC of 62XXXXX and newer. The LTC is printed on the top of the package as shown in Table 9-1 Nomenclature Description. The date code is encoded as YMXXXXX where Y=Year (6=2026) and M=Month in Hex (2=February).
Table 6-2 Device Operating Performance Points
OPP A53SS(1) C7/MMA FIXED OPERATING FREQUENCY OPTIONS (MHz)(2) MT/s(3)
R5FSS0 MAIN DOMAIN SYSCLK MCU R5F MCU DOMAIN SYSCLK DEVICE MGR R5F DEVICE MGR DOMAIN CLK HSM GPU VPAC DMPAC VPU LPDDR4
 
High
 		 From PLL BP to Speed Grade Max From PLL BP to Speed Grade Max 800 500 800 400 800 400 400 Speed Grade Max 600 428.5 500,
400,
200,
or
100		 From PLL BP(4) to Speed Grade Max
 
Low
 		 400 250 400 200 400 133 133
(1) Default operating frequency, set by software at boot. Supports Dynamic Frequency Scaling after boot.
(2) Fixed operating frequency, set by software at boot.
(3) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation. Refer to LPDDR4 Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency.
(4) The DDR PLL output, which sources DDR0_CK0 and DDR0_CK0_n, is typically defined in units of frequency. So the "DDR PLL Bypass" transaction rate is equal to 2x the DDR PLL output frequency when operating in bypass mode.