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TDA4VEN-Q1

ACTIVE

SoC with Quad Arm® Cortex®-A53, 4 TOPS of AI, C7xDSP, and GPU for vision perception and analytics

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TDA4VEN-Q1

ACTIVE
Data sheet Order now

Product details

CPU 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 DSI, MIPI DPI, OLDI Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Hardware accelerators C7™ NPU, Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system AutoSAR, FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Secure boot TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution TPS65224-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled Edge AI Studio enabled, Yes
CPU 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 DSI, MIPI DPI, OLDI Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Hardware accelerators C7™ NPU, Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system AutoSAR, FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Secure boot TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution TPS65224-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled Edge AI Studio enabled, Yes
FCBGA (AMW) 594 324 mm² 18 x 18

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Run-time Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Two Deep Learning Accelerators (up to 4 TOPS total), each with:
    • C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at up to 1.0GHz
    • Matrix Multiply Accelerator (MMA), up to 2 TOPS (8b) at up to 1.0GHz
    • 64KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
    • 2.25MB of L2 SRAM with SECDED ECC
  • Depth and Motion Processing Accelerators (DMPAC)
    • Dense Optical Flow (DOF) Accelerator
    • Stereo Disparity Engine (SDE) Accelerator
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
    • 600 MP/s ISP
    • Support for 12-bit RGB-IR
    • Support for up to 16-bit input RAW format
    • Line support up to 4096
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
      • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem
    • Triple display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
      • OLDI-SL (Single Link): up to 1920 x 1080 at 60fps (165-MHz Pixel Clock)
      • OLDI-DL (Dual Link): up to 3840 x 1080 at 60fps (150-MHz Pixel Clock)
      • MIPI DSI: with 4 Lane MIPI® D-PHY supports up to 3840 x 1080 at 60fps (300-MHz Pixel Clock)
      • DPI (24-bit RGB parallel interface): up to 1920 x 1080 at 60fps (165-MHz pixel clock)
    • Four display pipelines with hardware overlay support. A maximum of two display pipelines may be used per display.
    • Supports safety features such as freeze frame detection and data correctness check
  • 3D Graphics Processing Unit (TDA4VEN)
    • IMG BXS-4-64 with 256KB cache
    • Up to 50 GFLOPS
    • Single shader core
    • OpenGL ES3.2 and Vulkan 1.2 API support
  • Four Camera Serial Interface (CSI-2) Receiver with 4 Lane D-PHY
    • MIPI® CSI-2 v1.3 Compliant + MIPI® D-PHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
  • One CSI2.0 Transmitter with 4 Lane D-PHY (shared with MIPI DSI)
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Up to 500 MP/s decode/encode support (4K60)
  • Motion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)

Memory Subsystem:

  • On-chip RAM dedicated to key processing cores
    • 256KB of On-Chip RAM (OCRAM) with SECDED ECC
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Device Manager Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Run-time Manager Subsystem
    • 2.25MB of L2 SRAM with SECDED ECC in each C7x Deep Learning Accelerator (up to 4.5MB total)
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4 memory types
    • 32-bit data bus with inline ECC
    • Supports speeds up to 4000 MT/s
    • Max LPDDR4 size of 8GB

Functional Safety:

  • Functional Safety-Compliant targeted for Automotive (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 planned
  • AEC - Q100 qualified

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
  • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • PCI-Express Gen3 single lane controller (PCIE)
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000) or SGMII (1Gbps)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • USB3.1-Gen1 Port
    • One enhanced SuperSpeed Gen1 port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device
    • Integrated USB VBUS detection
  • USB2.0 Port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity and Automotive interfaces:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 7x Inter-Integrated Circuit (I2C) ports
  • 5x Multichannel Audio Serial Ports (McASP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 4x Controller Area Network (CAN) modules with CAN-FD support

Media and Data Storage:

  • 3x Secure Digital (SD) (4b+4b+8b) interfaces
    • 1x 8-bit eMMC interface up to HS400 speed
    • 2x 4-bit SD/SDIO interfaces up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Technology / Package:

  • 16-nm FinFET technology
  • 18 mm x 18 mm, 0.65-mm pitch with VCA, 594-pin FCBGA (AMW)

Companion Power Management Solution:

  • Functional Safety-Compliant support up to ASIL-B or SIL-2 targeted
  • TPS6522x PMIC
  • TPS6287x Stackable, Fast Transient Bucks

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Run-time Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Two Deep Learning Accelerators (up to 4 TOPS total), each with:
    • C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at up to 1.0GHz
    • Matrix Multiply Accelerator (MMA), up to 2 TOPS (8b) at up to 1.0GHz
    • 64KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
    • 2.25MB of L2 SRAM with SECDED ECC
  • Depth and Motion Processing Accelerators (DMPAC)
    • Dense Optical Flow (DOF) Accelerator
    • Stereo Disparity Engine (SDE) Accelerator
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
    • 600 MP/s ISP
    • Support for 12-bit RGB-IR
    • Support for up to 16-bit input RAW format
    • Line support up to 4096
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
      • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem
    • Triple display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
      • OLDI-SL (Single Link): up to 1920 x 1080 at 60fps (165-MHz Pixel Clock)
      • OLDI-DL (Dual Link): up to 3840 x 1080 at 60fps (150-MHz Pixel Clock)
      • MIPI DSI: with 4 Lane MIPI® D-PHY supports up to 3840 x 1080 at 60fps (300-MHz Pixel Clock)
      • DPI (24-bit RGB parallel interface): up to 1920 x 1080 at 60fps (165-MHz pixel clock)
    • Four display pipelines with hardware overlay support. A maximum of two display pipelines may be used per display.
    • Supports safety features such as freeze frame detection and data correctness check
  • 3D Graphics Processing Unit (TDA4VEN)
    • IMG BXS-4-64 with 256KB cache
    • Up to 50 GFLOPS
    • Single shader core
    • OpenGL ES3.2 and Vulkan 1.2 API support
  • Four Camera Serial Interface (CSI-2) Receiver with 4 Lane D-PHY
    • MIPI® CSI-2 v1.3 Compliant + MIPI® D-PHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
  • One CSI2.0 Transmitter with 4 Lane D-PHY (shared with MIPI DSI)
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Up to 500 MP/s decode/encode support (4K60)
  • Motion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)

Memory Subsystem:

  • On-chip RAM dedicated to key processing cores
    • 256KB of On-Chip RAM (OCRAM) with SECDED ECC
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Device Manager Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Run-time Manager Subsystem
    • 2.25MB of L2 SRAM with SECDED ECC in each C7x Deep Learning Accelerator (up to 4.5MB total)
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4 memory types
    • 32-bit data bus with inline ECC
    • Supports speeds up to 4000 MT/s
    • Max LPDDR4 size of 8GB

Functional Safety:

  • Functional Safety-Compliant targeted for Automotive (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 planned
  • AEC - Q100 qualified

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
  • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • PCI-Express Gen3 single lane controller (PCIE)
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000) or SGMII (1Gbps)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • USB3.1-Gen1 Port
    • One enhanced SuperSpeed Gen1 port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device
    • Integrated USB VBUS detection
  • USB2.0 Port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity and Automotive interfaces:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 7x Inter-Integrated Circuit (I2C) ports
  • 5x Multichannel Audio Serial Ports (McASP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 4x Controller Area Network (CAN) modules with CAN-FD support

Media and Data Storage:

  • 3x Secure Digital (SD) (4b+4b+8b) interfaces
    • 1x 8-bit eMMC interface up to HS400 speed
    • 2x 4-bit SD/SDIO interfaces up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Technology / Package:

  • 16-nm FinFET technology
  • 18 mm x 18 mm, 0.65-mm pitch with VCA, 594-pin FCBGA (AMW)

Companion Power Management Solution:

  • Functional Safety-Compliant support up to ASIL-B or SIL-2 targeted
  • TPS6522x PMIC
  • TPS6287x Stackable, Fast Transient Bucks

The TDA4VEN/TDA4AEN (aka, TDA4-Entry) processor family is an extension of the Jacinto™ 7 automotive-grade family of heterogeneous Arm® processors targeted at Advanced Driver Assistance System (ADAS) applications. With embedded Deep Learning (DL), Video, Vision Processing, and 3D Graphics acceleration, display interface and extensive automotive peripheral and networking options, TDA4VEN/TDA4AEN is built for a set of cost and power sensitive automotive applications such as NCAP front camera or entry-level park assistance systems. The cost optimized TDA4VEN/TDA4AEN provides an optimized performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in stand-alone Electronic Control Units (ECUs).

TDA4VEN/TDA4AEN contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL), Dense Optical Flow (DOF) video and 3D Graphics accelerators, a Cortex®-R5F MCU Island core and two Cortex®-R5F cores for Device and Run-time Management. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based algorithms. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include TI’s Dense Optical Flow (DOF) accelerator as well two “C7x” next generation DSP with scalar and vector cores, dedicated “MMA” deep learning accelerator combined with a large 2.25MB L2 memory enabling performance up to 4 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.

TDA4VEN/TDA4AEN integrates high-speed IOs including a PCIe Gen-3 (1L) and 3-port Gigabit Ethernet switch with one internal port and two external ports with TSN support. In addition, an extensive peripherals set is included in TDA4VEN/TDA4AEN to enable system level connectivity such as USB, MMC/SD, four CSI2.0 Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. TDA4VEN/TDA4AEN supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and employs advanced power management support for power-sensitive applications. Integrated diagnostics and safety features support operations up to ASIL-B at SoC level, (ASIL-D systematic level).

The TDA4VEN/TDA4AEN (aka, TDA4-Entry) processor family is an extension of the Jacinto™ 7 automotive-grade family of heterogeneous Arm® processors targeted at Advanced Driver Assistance System (ADAS) applications. With embedded Deep Learning (DL), Video, Vision Processing, and 3D Graphics acceleration, display interface and extensive automotive peripheral and networking options, TDA4VEN/TDA4AEN is built for a set of cost and power sensitive automotive applications such as NCAP front camera or entry-level park assistance systems. The cost optimized TDA4VEN/TDA4AEN provides an optimized performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in stand-alone Electronic Control Units (ECUs).

TDA4VEN/TDA4AEN contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL), Dense Optical Flow (DOF) video and 3D Graphics accelerators, a Cortex®-R5F MCU Island core and two Cortex®-R5F cores for Device and Run-time Management. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based algorithms. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include TI’s Dense Optical Flow (DOF) accelerator as well two “C7x” next generation DSP with scalar and vector cores, dedicated “MMA” deep learning accelerator combined with a large 2.25MB L2 memory enabling performance up to 4 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.

TDA4VEN/TDA4AEN integrates high-speed IOs including a PCIe Gen-3 (1L) and 3-port Gigabit Ethernet switch with one internal port and two external ports with TSN support. In addition, an extensive peripherals set is included in TDA4VEN/TDA4AEN to enable system level connectivity such as USB, MMC/SD, four CSI2.0 Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. TDA4VEN/TDA4AEN supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and employs advanced power management support for power-sensitive applications. Integrated diagnostics and safety features support operations up to ASIL-B at SoC level, (ASIL-D systematic level).
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet TDA4VEN, TDA4AEN Jacinto™ Processors datasheet (Rev. B) PDF | HTML 26 Mar 2026
* Errata J722S TDA4VEN TDA4AEN AM67 Processor Silicon Revision 1.0 Errata (Rev. A) PDF | HTML 15 Apr 2025
* User guide J722S TDA4VEN TDA4AEN AM67 Processor Silicon Revision 1.0 Technical Reference Manual (Rev. C) PDF | HTML 25 Nov 2025
Product overview TIDLRunner: Simplifying the 'Bring Your Own Model' Development Flow for Edge AI Accelerated Processors PDF | HTML 14 May 2026
White paper Securing the Future: Cyber Resilience Act (EU-CRA) Compliance with TI’s Jacinto and Sitara Processors PDF | HTML 24 Apr 2026
Application note Memory allocation for TIDL usage PDF | HTML 10 Nov 2025
Functional safety information J721E, J721S2, J7200, J784S4, and J742S2 TÜV SÜD Letter of Confirmation for Software Component Qualification 01 Oct 2025
Functional safety information J7200, J721E, J721S2, J722S, J742S2, and J784S4 SDL TÜV SÜD Functional Safety Certificate (Rev. A) 25 Sep 2025
Functional safety information TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. D) 17 Jun 2025
Application note MCAN Debug Guide PDF | HTML 18 Feb 2025
Application note Microcontroller Abstraction Layer on Jacinto™ and Sitara™ Embedded Processors PDF | HTML 28 Jan 2025
Application brief Custom DDR Memory Mapping for Vision Applications on Jacinto SoCs PDF | HTML 16 Dec 2024
User guide J722S/TDA4VEN/TDA4AEN/AM67 Power Estimation Tool User’s Guide (Rev. A) 03 Oct 2024
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 05 Aug 2024
Application note Debugging GPU Driver Issues on TDA4x and AM6x Devices PDF | HTML 20 Jun 2024
Application note Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 04 Jun 2024
Product overview J722S/AM67x/TDA4VEN/TDA4AEN Processor Automotive Power Designs using TPS6522312-Q1 PMIC PDF | HTML 18 Apr 2024
Application note Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 04 Apr 2024
Application note Jacinto7 HS Device Customer Return Process PDF | HTML 16 Nov 2023
White paper 以高度整合處理器設計高效邊緣 AI 系統 (Rev. A) PDF | HTML 19 Apr 2023
White paper 고도로 통합된 프로세서를 사용해 효 율적인 에지 AI 시스템 설계 (Rev. A) PDF | HTML 19 Apr 2023
White paper Designing an Efficient Edge AI System with Highly Integrated Processors (Rev. A) PDF | HTML 13 Mar 2023
Application note UART Log Debug System on Jacinto 7 SoC PDF | HTML 09 Jan 2023
Product overview Jacinto™ 7 Safety Product Overview PDF | HTML 15 Aug 2022
Application note Dual-TDA4x System Solution PDF | HTML 29 Apr 2022
Application note SPI Enablement & Validation on TDA4 Family PDF | HTML 05 Apr 2022
Technical article How are sensors and processors creating more intelligent and autonomous robots? PDF | HTML 29 Mar 2022
Technical article How to simplify your embedded edge AI application development PDF | HTML 28 Jan 2022
Application note Enabling MAC2MAC Feature on Jacinto7 Soc 10 Jan 2022
Functional safety information Leverage Jacinto 7 Processors Functional Safety Features for Automotive Designs (Rev. A) PDF | HTML 13 Oct 2021
Application note TDA4 Flashing Techniques PDF | HTML 08 Jul 2021
White paper Jacinto™ 7 프로세서의 보안 구현 도구 04 Jan 2021
White paper Security Enablers on Jacinto™ 7 Processors 04 Jan 2021
White paper Sicherheitsaktivierung auf Jacinto™ 7-Prozessoren 04 Jan 2021
White paper Differenzierungsmöglichkeit durch MCU-Integration Prozessoren der Reihe Jacinto™ 22 Oct 2020
White paper Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors 22 Oct 2020
White paper Jacinto™ 7 프로세서의 MCU 통합으로 차별화 지원 22 Oct 2020
Application note OSPI Tuning Procedure PDF | HTML 08 Jul 2020

Design & development

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Evaluation board

J722SXH01EVM — TDA4VEN, TDA4AEN and AM67 evaluation module

The J722SXH01EVM starter kit evaluation module is built around our J722S, TDA4VEN, TDA4AEN and AM67 vision and display processor, which includes scalable Arm® Cortex®-A53 performance, image signal processor supporting up to 600MP/s, up to 4 tera-operations-per-second AI (...)

User guide: PDF | HTML
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ALTOS-3P-V2 — Altos four-chip cascaded imaging radar based on TDA4 processor

Altos Radar is the world’s leading imaging radar developer for automotive applications. 

 

The Altos V2 is a four-chip cascaded imaging radar design that is based on TI AWR2243 MMIC and TDA4 processor. It features a customized 12TX and 16TX antenna array design, complete signal processing pipeline, (...)

From: Altos Radar Inc.
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Debug probe

TMDSEMU110-U — XDS110 JTAG Debug Probe

The Texas Instruments XDS110 is a new class of debug probe (emulator) for TI embedded processors. The XDS110 replaces the XDS100 family while supporting a wider variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a single pod. Also, all XDS debug probes support Core and System Trace in all (...)

User guide: PDF
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Debug probe

LB-3P-TRACE32-ARM — Lauterbach TRACE32® Debug and Trace System for Arm®-based Microcontrollers and Processors

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of Arm®-based microcontrollers and processors. The globally renowned debug and trace solutions for embedded systems and SoCs are the perfect (...)

From: Lauterbach GmbH
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Debug probe

TSK-3P-BLUEBOX — TASKING BlueBox hardware debugger

TASKING’s Debug, Trace, and Test tools offer comprehensive solutions for efficient debugging, tracing, and testing of TI's embedded systems. The scalable TASKING BlueBox debuggers allow users to easily flash, debug, and test across TI's portfolio. Development on TI hardware is made even easier with (...)

From: TASKING Germany GmbH
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Software development kit (SDK)

PROCESSOR-SDK-LINUX-J722S — Processor SDK Linux for J722S

The J722S processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4VEN-Q1 and TDA4AEN-Q1 system-on-a-chip (SoCs) within our Jacinto™ platform.

(...)
Supported products & hardware

Supported products & hardware
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Software development kit (SDK)

PROCESSOR-SDK-QNX-J722S — Processor SDK QNX for J722S

The J722S processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4VEN-Q1 and TDA4AEN-Q1 system-on-a-chip (SoCs) within our Jacinto™ platform.

(...)
Supported products & hardware

Supported products & hardware
Download options
Software development kit (SDK)

PROCESSOR-SDK-RTOS-J722S — Processor SDK RTOS for J722S

The J722S processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4VEN-Q1 and TDA4AEN-Q1 system-on-a-chip (SoCs) within our Jacinto™ platform.

(...)
Supported products & hardware

Supported products & hardware
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Firmware

USIT-3P-SECIC-HSM — Uni-Sentry SecIC-HSM Firmware

The SecIC-HSM is designed to meet the cybersecurity requirements needed for MCU/SoC chips. The HSM firmware can be applied in fields such as automobiles, new energy, photovoltaics, robotics, healthcare, and aviation. The provided cybersecurity functions available include secure boot, secure (...)
From: Shanghai Uni-Sentry Intelligent Technology Co., LTD
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Firmware

USIT-3P-SECIC-PQC — Uni-Sentry SecIC-PQC Algorithms Firmware

Uni-Sentry's security solutions adopt PQC algorithms capable of resisting decryption threats posed by quantum computers to traditional cryptographic algorithms. The PQC firmware is co-optimized with Hardware Security Module (HSM), leveraging hardware acceleration and security enhancement to improve (...)
From: Shanghai Uni-Sentry Intelligent Technology Co., LTD
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IDE, configuration, compiler or debugger

CCSTUDIO — CCStudio™ IDE

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

Supported products & hardware

Supported products & hardware
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IDE, configuration, compiler or debugger

DDR-CONFIG-J722S — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
Supported products & hardware

Supported products & hardware
Launch
IDE, configuration, compiler or debugger

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

Supported products & hardware

Supported products & hardware
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Operating system (OS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The INTEGRITY RTOS from Green Hills Software is the safe and secure foundation for running critical applications and guest operating systems on TI processors using Arm® Cortex-A cores. Its certified separation kernel runs software within protected partitions with certified (...)
From: Green Hills Software
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Operating system (OS)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
From: Green Hills Software
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Operating system (OS)

WHIS-3P-SAFERTOS — WITTENSTEIN SAFERTOS Pre-certified safety RTOS

SAFERTOS® is a unique real time operating system designed for embedded processors. It is precertified to IEC 61508 SIL3 and ISO 26262 ASILD standards by TÜV SÜD. SAFERTOS® was crafted specifically for safety by WHIS' team of experts and is used globally in safety critical applications. WHIS and (...)
From: WITTENSTEIN High Integrity Systems
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Simulation model

J722S BSDL Model

SPRM854.ZIP (12 KB) - BSDL Model
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Simulation model

J722S IBIS Model

SPRM855.ZIP (4140 KB) - IBIS Model
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Simulation model

J722S Thermal Model

SPRM856.ZIP (0 KB) - Thermal Model
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Gerber file

J722S/AM67x/TDA4VEN/TDA4AEN Evaluation Module Design Files (Rev. C)

SPRR495C.ZIP (556217 KB)
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Package Pins CAD symbols, footprints & 3D models
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