SPRSP96B March   2024  – March 2026 TDA4AEN-Q1 , TDA4VEN-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      10
      2.      11
    3. 5.3 Signal Descriptions
      1.      13
      2. 5.3.1  CPSW3G
        1. 5.3.1.1 MAIN Domain
          1.        16
          2.        17
          3.        18
          4.        19
      3. 5.3.2  CPTS
        1. 5.3.2.1 MAIN Domain
          1.        22
      4. 5.3.3  CSI-2
        1. 5.3.3.1 MAIN Domain
          1.        25
          2.        26
          3.        27
          4.        28
      5. 5.3.4  DDRSS
        1. 5.3.4.1 MAIN Domain
          1.        31
      6. 5.3.5  DSI
        1. 5.3.5.1 MAIN Domain
          1.        34
      7. 5.3.6  DSS
        1. 5.3.6.1 MAIN Domain
          1.        37
      8. 5.3.7  ECAP
        1. 5.3.7.1 MAIN Domain
          1.        40
          2.        41
          3.        42
      9. 5.3.8  Emulation and Debug
        1. 5.3.8.1 MAIN Domain
          1.        45
        2. 5.3.8.2 MCU Domain
          1.        47
      10. 5.3.9  EPWM
        1. 5.3.9.1 MAIN Domain
          1.        50
          2.        51
          3.        52
          4.        53
      11. 5.3.10 EQEP
        1. 5.3.10.1 MAIN Domain
          1.        56
          2.        57
          3.        58
      12. 5.3.11 GPIO
        1. 5.3.11.1 MAIN Domain
          1.        61
          2.        62
        2. 5.3.11.2 MCU Domain
          1.        64
      13. 5.3.12 GPMC
        1. 5.3.12.1 MAIN Domain
          1.        67
      14. 5.3.13 I2C
        1. 5.3.13.1 MAIN Domain
          1.        70
          2.        71
          3.        72
          4.        73
          5.        74
        2. 5.3.13.2 MCU Domain
          1.        76
        3. 5.3.13.3 WKUP Domain
          1.        78
      15. 5.3.14 MCAN
        1. 5.3.14.1 MAIN Domain
          1.        81
          2.        82
        2. 5.3.14.2 MCU Domain
          1.        84
          2.        85
      16. 5.3.15 MCASP
        1. 5.3.15.1 MAIN Domain
          1.        88
          2.        89
          3.        90
          4.        91
          5.        92
      17. 5.3.16 MCSPI
        1. 5.3.16.1 MAIN Domain
          1.        95
          2.        96
          3.        97
        2. 5.3.16.2 MCU Domain
          1.        99
          2.        100
      18. 5.3.17 MDIO
        1. 5.3.17.1 MAIN Domain
          1.        103
      19. 5.3.18 MMC
        1. 5.3.18.1 MAIN Domain
          1.        106
          2.        107
          3.        108
      20. 5.3.19 OLDI
        1. 5.3.19.1 MAIN Domain
          1.        111
      21. 5.3.20 OSPI
        1. 5.3.20.1 MAIN Domain
          1.        114
      22. 5.3.21 Power Supply
        1.       116
      23. 5.3.22 Reserved
        1.       118
      24. 5.3.23 SERDES
        1. 5.3.23.1 MAIN Domain
          1.        121
          2.        122
          3.        123
      25. 5.3.24 System and Miscellaneous
        1. 5.3.24.1 Boot Mode Configuration
          1. 5.3.24.1.1 MAIN Domain
            1.         127
        2. 5.3.24.2 Clock
          1. 5.3.24.2.1 MCU Domain
            1.         130
          2. 5.3.24.2.2 WKUP Domain
            1.         132
        3. 5.3.24.3 System
          1. 5.3.24.3.1 MAIN Domain
            1.         135
          2. 5.3.24.3.2 MCU Domain
            1.         137
          3. 5.3.24.3.3 WKUP Domain
            1.         139
        4. 5.3.24.4 VMON
          1.        141
      26. 5.3.25 TIMER
        1. 5.3.25.1 MAIN Domain
          1.        144
        2. 5.3.25.2 MCU Domain
          1.        146
        3. 5.3.25.3 WKUP Domain
          1.        148
      27. 5.3.26 UART
        1. 5.3.26.1 MAIN Domain
          1.        151
          2.        152
          3.        153
          4.        154
          5.        155
          6.        156
          7.        157
        2. 5.3.26.2 MCU Domain
          1.        159
        3. 5.3.26.3 WKUP Domain
          1.        161
      28. 5.3.27 USB
        1. 5.3.27.1 MAIN Domain
          1.        164
          2.        165
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings for AEC - Q100 Qualified Devices in the AMW Package
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Power Consumption Summary
    7. 6.7  Electrical Characteristics
      1. 6.7.1  I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.7.2  Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.7.3  High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.7.4  Low-Frequency Oscillator (LFXOSC) Electrical Characteristics
      5. 6.7.5  eMMCPHY Electrical Characteristics
      6. 6.7.6  SDIO Electrical Characteristics
      7. 6.7.7  LVCMOS Electrical Characteristics
      8. 6.7.8  OLDI LVDS (OLDI) Electrical Characteristics
      9. 6.7.9  CSI-2 (D-PHY) Electrical Characteristics
      10. 6.7.10 DSI (D-PHY) Electrical Characteristics
      11. 6.7.11 USB2PHY Electrical Characteristics
      12. 6.7.12 SerDes PHY Electrical Characteristics
      13. 6.7.13 DDR Electrical Characteristics
    8. 6.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.8.2 Hardware Requirements
      3. 6.8.3 Programming Sequence
      4. 6.8.4 Impact to Your Hardware Warranty
    9. 6.9  Thermal Resistance Characteristics
      1. 6.9.1 Thermal Resistance Characteristics for AMW Package
    10. 6.10 Temperature Sensor Characteristics
    11. 6.11 Timing and Switching Characteristics
      1. 6.11.1 Timing Parameters and Information
      2. 6.11.2 Power Supply Requirements
        1. 6.11.2.1 Power Supply Slew Rate Requirement
        2. 6.11.2.2 Power Supply Sequencing
          1. 6.11.2.2.1 Power-Up Sequencing
          2. 6.11.2.2.2 Power-Down Sequencing
          3. 6.11.2.2.3 Partial IO Power Sequencing
      3. 6.11.3 System Timing
        1. 6.11.3.1 Reset Timing
        2. 6.11.3.2 Error Signal Timing
        3. 6.11.3.3 Clock Timing
      4. 6.11.4 Clock Specifications
        1. 6.11.4.1 Input Clocks / Oscillators
          1. 6.11.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 6.11.4.1.1.1 Load Capacitance
            2. 6.11.4.1.1.2 Shunt Capacitance
          2. 6.11.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
          3. 6.11.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source
          4. 6.11.4.1.4 WKUP_LFOSC0 LVCMOS Digital Clock Source
          5. 6.11.4.1.5 WKUP_LFOSC0 Not Used
        2. 6.11.4.2 Output Clocks
        3. 6.11.4.3 PLLs
        4. 6.11.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.11.5 Peripherals
        1. 6.11.5.1  ATL
          1. 6.11.5.1.1 ATL_PCLK Timing Requirements
          2. 6.11.5.1.2 ATL_AWS[x] Timing Requirements
          3. 6.11.5.1.3 ATL_BWS[x] Timing Requirements
          4. 6.11.5.1.4 ATCLK[x] Switching Characteristics
        2. 6.11.5.2  CPSW3G
          1. 6.11.5.2.1 CPSW3G MDIO Timing
          2. 6.11.5.2.2 CPSW3G RMII Timing
          3. 6.11.5.2.3 CPSW3G RGMII Timing
        3. 6.11.5.3  CPTS
        4. 6.11.5.4  CSI-2
        5. 6.11.5.5  CSI-2 TX
        6. 6.11.5.6  DDRSS
        7. 6.11.5.7  DSI
        8. 6.11.5.8  DSS
        9. 6.11.5.9  ECAP
        10. 6.11.5.10 Emulation and Debug
          1. 6.11.5.10.1 Trace
          2. 6.11.5.10.2 JTAG
        11. 6.11.5.11 EPWM
        12. 6.11.5.12 EQEP
        13. 6.11.5.13 GPIO
        14. 6.11.5.14 GPMC
          1. 6.11.5.14.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.11.5.14.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.11.5.14.3 GPMC and NAND Flash — Asynchronous Mode
        15. 6.11.5.15 I2C
        16. 6.11.5.16 MCAN
        17. 6.11.5.17 MCASP
        18. 6.11.5.18 MCSPI
          1. 6.11.5.18.1 MCSPI — Controller Mode
          2. 6.11.5.18.2 MCSPI — Peripheral Mode
        19. 6.11.5.19 MMCSD
          1. 6.11.5.19.1 MMC0 - eMMC Interface
            1. 6.11.5.19.1.1  Legacy SDR Mode
            2. 6.11.5.19.1.2  High Speed SDR Mode
            3. 6.11.5.19.1.3  High Speed DDR Mode
            4. 6.11.5.19.1.4  HS200 Mode
            5. 6.11.5.19.1.5  HS400 Mode
            6. 6.11.5.19.1.6  UHS–I SDR12 Mode
            7. 6.11.5.19.1.7  UHS–I SDR25 Mode
            8. 6.11.5.19.1.8  UHS–I SDR50 Mode
            9. 6.11.5.19.1.9  UHS–I DDR50 Mode
            10. 6.11.5.19.1.10 UHS–I SDR104 Mode
          2. 6.11.5.19.2 MMC1/MMC2 - SD/SDIO Interface
            1. 6.11.5.19.2.1 Default Speed Mode
            2. 6.11.5.19.2.2 High Speed Mode
            3. 6.11.5.19.2.3 UHS–I SDR12 Mode
            4. 6.11.5.19.2.4 UHS–I SDR25 Mode
            5. 6.11.5.19.2.5 UHS–I SDR50 Mode
            6. 6.11.5.19.2.6 UHS–I DDR50 Mode
            7. 6.11.5.19.2.7 UHS–I SDR104 Mode
        20. 6.11.5.20 OLDI
          1. 6.11.5.20.1 OLDI0 Switching Characteristics
        21. 6.11.5.21 OSPI
          1. 6.11.5.21.1 OSPI0 PHY Mode
            1. 6.11.5.21.1.1 OSPI0 With PHY Data Training
            2. 6.11.5.21.1.2 OSPI0 Without Data Training
              1. 6.11.5.21.1.2.1 OSPI0 PHY SDR Timing
              2. 6.11.5.21.1.2.2 OSPI0 PHY DDR Timing
          2. 6.11.5.21.2 OSPI0 Tap Mode
            1. 6.11.5.21.2.1 OSPI0 Tap SDR Timing
            2. 6.11.5.21.2.2 OSPI0 Tap DDR Timing
        22. 6.11.5.22 PCIe
        23. 6.11.5.23 Timers
        24. 6.11.5.24 UART
        25. 6.11.5.25 USB
  8. 7 Detailed Description
    1. 7.1 Overview
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Supply Designs
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 LPDDR4 Board Design and Layout Guidelines
      2. 8.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (only available in Octal SPI devices)
      3. 8.2.3 USB VBUS Design Guidelines
      4. 8.2.4 System Power Supply Monitor Design Guidelines
      5. 8.2.5 High Speed Differential Signal Routing Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

10 Revision History

Changes from September 30, 2024 to March 27, 2026 (from Revision A (September 2024) to Revision B (March 2026))

  • (Features, Deep Learning Accelerators): Updated the swapped C7x DSP L1 DCache and L1 ICache memory sizesGo
  • (Features): Updated decode/encode support up to 500 MP/sGo
  • (Device Comparison): Added the JTAG User ID register bit field [WKUP_CTRL_MMR_CFG0_JTAG_USER_ID[31:16] "DEVICE_ID"]; associated the DEVICE_ID bit field values per GPN; plus, added/changed the associated footnotesGo
  • (Pin Attributes): Updated "Type" column information for MMC1_* pinsGo
  • (Pin Attributes): Removed unsupported GPIO1_72 mux mode from PCIE0_CLKREQn pinGo
  • (Pin Attributes): Updated "4L_PHY" IO buffer type to "SERDES"Go
  • (Signal Descriptions - Global): Changed "PIN TYPE" to "SIGNAL TYPE" in the header of each Signal Description tableGo
  • (GPIO1 Signal Descriptions): Removed unsupported GPIO1_72 signalGo
  • (MMC2 Signal Descriptions): Added MMC2_SDCSD and MMC2_SDWP signals footnoteGo
  • (OLDI0 Signal Descriptions): Added GPIO functionality footnote for OLDI pinsGo
  • (System Signal Descriptions): Updated signal descriptions for OBSCLK0 and OBSCLK1Go
  • (MCU System Signal Descriptions): Updated signal description for MCU_OBSCLK0Go
  • (UART1 Signal Descriptions): Updated UART1_DCDn signal description to match functionalityGo
  • (Connectivity Requirements): Updated the connectivity requirements table by adding additional signal names and their specific connection requirements for unconnected ballsGo
  • (Specifications): Removed note stating that specifications listed are preliminaryGo
  • (ESD Ratings for AEC - Q100 Qualified Devices in the AMW Package): Updated corner pins in the tableGo
  • (Recommended Operating Conditions): Added values for VDDA_3P3_USB1Go
  • (Device Speed Grades): Updated the J‑frequency speed grade for C7/MMA from 912.5 MHz to 1000 MHz, and added footnote (3) defining the Lot Trace Code (LTC)Go
  • (Device Operating Performance Points): Added additional table note regarding the DDR PLL BypassGo
  • (Power Consumption Summary): Added section with link to Power Estimation Tool and the corresponding Power Estimation Tool User’s GuideGo
  • (I2C Open-Drain, and Fail-Safe Electrical Characteristics) Added a table note to the Input Leakage Current parameterGo
  • (I2C Open-Drain, and Fail-Safe Electrical Characteristics) Separated the Input Leakage Current Test Conditions into two rowsGo
  • (Fail-Safe Reset Electrical Characteristics) Added a table note to the Input Leakage Current parameterGo
  • (Fail-Safe Reset Electrical Characteristics) Separated the Input Leakage Current Test Conditions into two rowsGo
  • (High-Frequency Oscillator Electrical Characteristics) Added a table note to the Input Leakage Current parameterGo
  • (High-Frequency Oscillator Electrical Characteristics) Separated the Input Leakage Current Test Conditions into two rowsGo
  • (Low-Frequency Oscillator Electrical Characteristics) Added a table note to the Input Leakage Current parameterGo
  • (Low-Frequency Oscillator Electrical Characteristics) Separated the Input Leakage Current Test Conditions into two rowsGo
  • (eMMCPHY Electrical Characteristics): Added the eMMCPHY Electrical Characteristics sectionGo
  • (SDIO Electrical Characteristics) Added a table note to the Input Leakage Current parameterGo
  • (SDIO Electrical Characteristics) Separated the Input Leakage Current Test Conditions into two rowsGo
  • (LVCMOS Electrical Characteristics) Added a table note to the Input Leakage Current parameterGo
  • (LVCMOS Electrical Characteristics) Separated the Input Leakage Current Test Conditions into two rowsGo
  • (OLDI LVDS (OLDI) Electrical Characteristics): Added the OLDI LVDS (OLDI) Electrical Characteristics sectionGo
  • (DSI (D-PHY) Electrical Characteristics): Added the DSI (D-PHY) Electrical Characteristics sectionGo
  • (SerDes PHY Electrical Characteristics): Added new section containing the relevant tableGo
  • (Recommended Operating Conditions for OTP eFuse Programming): Removed the OPP NOM (BOOT) reference from the VDD_CORE parameter descriptionGo
  • (Impact to Your Hardware Warranty): Updated/Changed the "Consequently, TI will have no …" sentence in the paragraphGo
  • (Thermal Resistance Characteristics for AMW Package): Removed "TBD" from the table nameGo
  • (Temperature Sensor Characteristics): Added new section to define Voltage and Temperature Module (VTM) on die temperature sensor characteristicsGo
  • (Power-Up Sequencing – Supply / Signal Assignments): Added missing power rails, VDDA_PLL3, VDDA_PLL4, and VDDA_TEMP2Go
  • (Power-Down Sequencing – Supply / Signal Assignments): Added missing power rails, VDDA_PLL3, VDDA_PLL4, and VDDA_TEMP2Go
  • (Input Clocks / Oscillators): Added VOUT0_EXTPCLKINGo
  • (MCU_OSC0 Switching Characteristics - Crystal Mode [Table]): Updated/Changed the XI and XO capacitance MAX valuesGo
  • (Output Clocks): Updated OBSCLK signal descriptionsGo
  • (PLLs): Updated the PLL names to include the number references used in the TRM. Added MAIN_PLL5 (VIDEO PLL) and MAIN_PLL7 (C7x PLL)Go
  • (CPTS): Updated reference name for the TRM section under the timing tables.Go
  • (CSI-2): Increased the data rate of CSI-2 from 1.5GBPS to 2.5GBPSGo
  • (CSI-2 TX): Updated/Changed "TBD" to have CSI-2 TX contentGo
  • (DSI): Added the DSI sectionGo
  • (ECAP – Timing Requirements and Switching Characteristics): Updated the clock source referenced in table note 1Go
  • (EPWM – Timing Requirements and Switching Characteristics): Updated the clock source referenced in table note 1Go
  • (EQEP – Timing Requirements): Updated the clock source referenced in table note 1Go
  • (GPMC and NOR Flash Timing Requirements — Synchronous Mode): Removed the GPMC_FCLK=100MHz column timing values and the associated not_div_by_1_mode timing values for GPMC_FCLK=133MHz. Simplified several parameter descriptions. Also removed two table notes, one that described register configuration for GPMC_FCLK selection, and another that described register configuration for div_by_1_modeGo
  • (GPMC and NOR Flash Switching Characteristics – Synchronous Mode): Removed the GPMC_FCLK=100MHz column timing values and the associated not_div_by_1_mode timing values for GPMC_FCLK=133MHz. Simplified several parameter descriptions. Changed the timing variable in parameters F3 and F11 to "D". Removed the "J" timing variable from the F15 and F17 parameters. Updated the table notesGo
  • (GPMC and NOR Flash Timing Requirements – Asynchronous Mode): Removed the MODE column and the table note that described register configuration for div_by_1_mode. Added the correct table note for parameter FA21 Go
  • (GPMC and NOR Flash Switching Characteristics – Asynchronous Mode): Removed the MODE column and redundant rows. Also removed the table note that described register configuration for div_by_1_modeGo
  • (GPMC and NAND Flash Timing Requirements – Asynchronous Mode): Removed the MODE column and the table note that described register configuration for div_by_1_modeGo
  • (GPMC and NAND Flash Switching Characteristics – Asynchronous Mode): Removed the MODE column and the table note that described register configuration for div_by_1_mode. Added table notes and associated reference links for timing variables B, C, D, E, F, G, H, I, K, L, and MGo
  • (I2C): Changed the supported speeds and exception descriptions so they are organized based on IO buffer type rather than I2C port instanceGo
  • (MCAN): Updated reference name for the TRM section under the timing tables.Go
  • (MCASP): Changed the IOSET note that explains timing limitations associated with valid pin combinationsGo
  • (MCSPI): Changed the IOSET note that explains timing limitations associated with valid pin combinationsGo
  • (MCSPI Switching Characteristics - Controller Mode): Changed all instances of MSPI to MCSPI in table notes 2, 3, 4, and 5Go
  • (MMC0 DLL Delay Mapping for all Timing Modes): Changed the register names. Changed the OTAPDLYEN, OTAPDLYSEL, SELDLYTXCLK values for Legacy SDR and High Speed SDR modes. Split the HS400 mode into two operating conditions based on VDD_CORE voltage. Changed the STRBSEL and OTAPDLYSEL delay values for HS400 modeGo
  • (HS200 Mode): Added "MMC0 Timing RequirementsGo
  • (MMC0 Timing Requirements – HS400 Mode): Removed the maximum values associated with parameters HS2003 and HS2004, and added a note explaining why these parameters are not applicableGo
  • (MMC0 Switching Characteristics – HS400 Mode): Changed the HS4006, HS4007, HS4008, HS4009, HS40010, and HS40011 parameter valuesGo
  • (MMC1/MMC2 DLL Delay Mapping for all Timing Modes): Changed the register names, and changed the OTAPDLYENA and OTAPDLYSEL values for Default Speed and High Speed modesGo
  • (MMC1/MMC2 DLL Delay Mapping for all Timing Modes): Removed the CLKBUFSEL column because this register bit field doesn't provide any functionGo
  • (OLDI): Added section OLDI with subsection OLDI0 Switching CharacteristicsGo
  • (OSPI0 DLL Delay Mapping for PHY Data Training): Added a delay value for the "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD" register bit fieldGo
  • (OSPI Switching Characteristics – PHY Data Training): Corrected the formulas associated with timing parameters O5 and O11Go
  • (OSPI0 DLL Delay Mapping for PHY SDR Timing Modes): Added a delay value for the "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD" register bit fieldGo
  • (OSPI0 Switching Characteristics – PHY SDR Mode): Corrected the formulas associated with timing parameters O10 and O11Go
  • (OSPI0 DLL Delay Mapping for PHY DDR Timing Modes): Added a delay value for the "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD" register bit field. Updated PHY_CONFIG_TX_DLL_DELAY_FLD and PHY_CONFIG_RX_DLL_DELAY_FLD delay valuesGo
  • (OSPI0 Switching Characteristics – PHY DDR Mode): Corrected the formulas associated with timing parameters O4 and O5Go
  • (Applications, Implementation, and Layout): Removed obsolated Thermal Solution Guidance sectionGo
  • (Power Supply Designs): Added Power Supply Designs sectionGo
  • (Power Distribution Network Implementation Guidance): Removed sectionGo
  • (Device Nomenclature): Removed "TBD" from the device nameGo