SPRUIM6A October   2018  – November 2020

 

  1. 1Introduction
    1. 1.1 Key Features
  2. 2AM65x IDK Overview
  3. 3Common Processor Board
    1. 3.1 Key Features
    2. 3.2 Functional Block Diagram
    3. 3.3 Overview of Common Processor Board
      1. 3.3.1  Clocking
        1. 3.3.1.1 RTC Clock
        2. 3.3.1.2 Maxwell SoC Clock
        3. 3.3.1.3 Ethernet PHY Clocks
        4. 3.3.1.4 SERDES Clock
      2. 3.3.2  Reset
      3. 3.3.3  Power Requirements
        1. 3.3.3.1 Power Input
        2. 3.3.3.2 Overvoltage and Undervoltage Protection Circuit
        3. 3.3.3.3 Voltage Supervisor
        4. 3.3.3.4 Current Monitoring
        5. 3.3.3.5 Power Supply
        6. 3.3.3.6 Power Sequencing
        7. 3.3.3.7 SoC Power
      4. 3.3.4  Configuration
        1. 3.3.4.1 Boot Modes
        2. 3.3.4.2 JTAG
          1. 3.3.4.2.1 Test Automation
        3. 3.3.4.3 UART Interface
      5. 3.3.5  Memory Interfaces
        1. 3.3.5.1 DDR4 Interface
        2. 3.3.5.2 MMC Interface
          1. 3.3.5.2.1 SDHC Interface
          2. 3.3.5.2.2 eMMC Interface
        3. 3.3.5.3 OSPI Interface
        4. 3.3.5.4 SPI NOR Flash Interface
        5. 3.3.5.5 Board ID EEPROM Interface
        6. 3.3.5.6 Boot EEPROM Interface
      6. 3.3.6  Ethernet Interface
        1. 3.3.6.1 Gigabit Ethernet PHY Default Configuration
        2. 3.3.6.2 Ethernet LEDs
      7. 3.3.7  LCD Display Interface
      8. 3.3.8  USB 2.0 Interface
      9. 3.3.9  CSI-2 Interface
      10. 3.3.10 Application Card Interface
      11. 3.3.11 SERDES Interface
      12. 3.3.12 GPMC/DSS Interface
      13. 3.3.13 I2C Interface
      14. 3.3.14 SPI Interface
      15. 3.3.15 Timer and Interrupt
        1. 3.3.15.1 Timer
        2. 3.3.15.2 Interrupt
      16. 3.3.16 Fan Connector
  4. 4IDK Application Card
    1. 4.1 Key Features
    2. 4.2 Overview of IDK Application Board
      1. 4.2.1 Application Card Connector
      2. 4.2.2 Profibus Interface
      3. 4.2.3 CAN Interface
      4. 4.2.4 Rotary Switch
      5. 4.2.5 Industrial I/O Terminal Connector
      6. 4.2.6 Ethernet Interface
      7. 4.2.7 Board ID Memory
      8. 4.2.8 Power Supply
  5. 5x2 Lane PCIe Personality Card
    1. 5.1 Key Features
    2. 5.2 Overview of PCIex2 Daughter Card
      1. 5.2.1 Personality Card Connectors
      2. 5.2.2 USB 2.0 Interface
      3. 5.2.3 PCIe Interface
      4. 5.2.4 x2 Lane PCIe Personality Card Clocking
      5. 5.2.5 Board ID EEPROM Interface
      6. 5.2.6 x2 Lane PCIe Personality Card Power
  6. 6Known Issues
    1. 6.1 Determining the Revision and Date Code for the EVM
    2. 6.2 Known Issues for the A, E4, and E3 Revision
      1. 6.2.1 Lack of Reset for I2C IO Expander
    3. 6.3 Known Issues for the E4 & E3 Revision
      1. 6.3.1 Changes Unique to the E4 Revision Modified for 2.0 Revision
    4. 6.4 Known Issues for the E3 Revision
      1. 6.4.1 Resonance Observed on the SoC Side of Some Filters Associated with VDDA_1V8
      2. 6.4.2 Additional LDO Power Supply Needed for VDDA_1P8_SERDES0
      3. 6.4.3 Length of the RESET Signal to the PCIE Connectors on the SERDES Daughter Card
      4. 6.4.4 The PORz_OUT and MCU_PORz_OUT Signals Go High During Power Sequencing
      5. 6.4.5 Orientation of the Current Monitoring Shunt Resistors
      6. 6.4.6 SD Card IO Supply Capacitance
      7. 6.4.7 PHY Resistor Strapping Changed to Disable EEE Mode
      8. 6.4.8 The I2C Address for the I2C Boot Memory changed to 0x52
  7. 7Configuring the PRG0 and PRG1 Ethernet Interface to MII
    1. 7.1 Ethernet PHY Initial Conditions and TX Clock Signal Change
      1. 7.1.1 Ethernet PHY0 Clock and Initial Condition for MII
      2. 7.1.2 Ethernet PHY1 Clock and Initial Condition for MII
      3. 7.1.3 Ethernet PHY2 Clock and Initial Condition for MII
      4. 7.1.4 Ethernet PHY3 Clock and Initial Condition for MII
    2. 7.2 Ethernet PHY and TX Data Signals Change
      1. 7.2.1 Ethernet PHY0 TX Data Signals for MII
      2. 7.2.2 Ethernet PHY1 TX Data Signals for MII
      3. 7.2.3 Ethernet PHY2 TX Data Signals for MII
      4. 7.2.4 Ethernet PHY3 TX Data Signals for MII
  8. 8Revision History

GPMC/DSS Interface

The GPMC/DSS interface from the AM65x processor is routed to the GPMC/DSS expansion connector. This connector can be used to install an HDMI or DP adapter daughter card. The connector can also be used to attach to a circuit using the GPMC address/data bus interface. The function of the pins is defined by the pinmux definition.

The following interfaces are available on the GPMC/DSS connector:

  • Multiplexed GPMC and DSS signals. The signals are at 3.3-V I/O level.
  • McASP1 interface signals to support HDMI audio. The MCASP1 signals are multiplexed with PRG0_RGMII1 signals. Resistor options are provided to select the required interface. The McASP1 signals are at 1.8-V I/O level.
  • MCU_I2C0 for configuration and control. The signals are at 3.3-V I/O level.
  • WKUP I2C to connect to card ID memory. The signals are at 3.3-V I/O level.
  • SPI1 interface for configuration and control. The signals are at 3.3-V I/O level.

The McAPS1 signals are multiplexed with the PRG0_RGMII signals of the application card. Resistor options are provided on the processor card to select the required interface, as shown in Figure 3-21. Refer to Table 3-32 for details.

The board supports an option to mount a 60-pin connector (QSH-030-01-L-D-A-K) or a 120-pin connector (QSH-060-01-L-D-A-K). These connector footprints are overlapped such that only one of them can be mounted. By default, the 60-pin connector is mounted.

GPMC/DSS, I2C, and USB 2.0 signals are connected to 60-pin connector (J36). The McASP1 signals are connected to the second half of the 120-pin connector. Thus, to access the McASP1 signals, the 60-pin should be unmounted and 120-pin connector should be mounted.

Table 3-32 HDMI/GPMC Connector (J35) Pin-out
Pin No.SignalDirection
1VOUT1_DATA23_Output
2VCC1V8Power
3VOUT1_DATA22Bidirectional
4VCC1V8Power
5VOUT1_DATA21Power
6NCNA
7VOUT1_DATA20Bidirectional
8CARDID_HDMI_A0Output
9VOUT1_DATA19Bidirectional
10CARDID_HDMI_A1Output
11VOUT_D18_BOOTMODE18Bidirectional
12CARDID_HDMI_A0Power
13VOUT_D17_BOOTMODE17Bidirectional
14NCNA
15VOUT_D16_BOOTMODE16Bidirectional
16PORZ_OUTOutput
17DGNDPower
18HDMI_GPMC_BRD_DETInput
19VOUT_D15_BOOTMODE15Bidirectional
20VOUT1_PCLKOutput
21VOUT_D14_BOOTMODE14Bidirectional
22DGNDPower
23VOUT_D13_BOOTMODE13Bidirectional
24VOUT1_VSYNCOutput
25VOUT_D12_BOOTMODE12Bidirectional
26VOUT1_HSYNC_TEST_HDROutput
27VOUT_D11_BOOTMODE11Bidirectional
28VOUT1_DE_TEST_HDROutput
29VOUT_D10_BOOTMODE10Bidirectional
30DGNDPower
31VOUT_D9_BOOTMODE9Bidirectional
32SOC_MCU_SCLOutput
33VOUT_D8_BOOTMODE8Bidirectional
34SOC_MCU_SDABidirectional
35DGNDPower
36DGNDPower
37VOUT_D7_BOOTMODE7Bidirectional
38GP1_TOUCH_EVTOutput
39VOUT_D6_BOOTMODE6Bidirectional
40CON_LCD_PWR_DNOutput
41VOUT_D5_BOOTMODE5Power
42SOC_SPI1_CS1Output
43VOUT_D4_BOOTMODE4Bidirectional
44SOC_SPI1_MOSIOutput
45VOUT_D3_BOOTMODE3Bidirectional
46SOC_SPI1_MISOInput
47VOUT_D2_BOOTMODE2Bidirectional
48SOC_SPI1_CLKOutput
49VOUT_D1_BOOTMODE1Bidirectional
50USB1_HDMI_GPMC_DRVBUSOutput
51VOUT_D0_BOOTMODE0Bidirectional
52USB1_HDMI_GPMC_DMBidirectional
53NCNA
54USB1_HDMI_GPMC_DPBidirectional
55VCC_5V0Power
56VCC3V3_IOPower
57VCC_5V0Power
58VCC3V3_IOPower
59VCC_5V0Power
60VCC3V3_IOPower
61NCNA
62NCNA
63NCNA
64NCNA
65NCNA
66NCNA
67NCNA
68NCNA
69NCNA
70NCNA
71NCNA
72NCNA
73NCNA
74NCNA
75NCNA
76NCNA
77NCNA
78NCNA
79NCNA
80NCNA
81NCNA
82NCNA
83NCNA
84NCNA
85NCNA
86NCNA
87NCNA
88NCNA
89NCNA
90NCNA
91NCNA
92NCNA
93NCNA
94NCNA
95NCNA
96NCNA
97NCNA
98NCNA
99NCNA
100NCNA
101NCNA
102NCNA
103NCNA
104NCNA
105MCASP1_AFSX_3V3IO
106NCNA
107MCASP1_AXR1_3V3IO
108NCNA
109MCASP1_ACLKX_3V3IO
110NCNA
111MCASP1_AHCLKX_3V3IO
112NCNA
113MCASP1_AXR0_3V3IO
114NCNA
115MCASP1_ACLKR_3V3IO
116NCNA
117MCASP1_AFSR_3V3IO
118NCNA
119MCASP1_AHCLKR_3V3IO
120NCNA