SPRUJ10D May   2022  – September 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Preface: Read This First
    1. 2.1 Sitara MCU+ Academy
    2. 2.2 If You Need Assistance
    3. 2.3 Important Usage Notes
  5. 2Kit Overview
    1. 3.1 Kit Contents
    2. 3.2 Key Features
    3. 3.3 Component Identification
    4. 3.4 BoosterPacks
    5. 3.5 Compliance
    6. 3.6 Security
  6. 3Board Setup
    1. 4.1 Power Requirements
      1. 4.1.1 Power Input Using USB Type-C Connector
      2. 4.1.2 Power Status LEDs
      3. 4.1.3 Power Tree
    2. 4.2 Push Buttons
    3. 4.3 Boot Mode Selection
  7. 4Hardware Description
    1. 5.1  Functional Block Diagram
    2. 5.2  GPIO Mapping
    3. 5.3  Reset
    4. 5.4  Clock
    5. 5.5  Memory Interface
      1. 5.5.1 QSPI
      2. 5.5.2 Board ID EEPROM
    6. 5.6  Ethernet Interface
      1. 5.6.1 Ethernet PHY #1 - CPSW RGMII/ICSSM
      2. 5.6.2 Ethernet PHY #2 - CPSW RGMII/ICSSM
      3. 5.6.3 LED Indication in RJ45 Connector
    7. 5.7  I2C
    8. 5.8  Industrial Application LEDs
    9. 5.9  SPI
    10. 5.10 UART
    11. 5.11 MCAN
    12. 5.12 FSI
    13. 5.13 JTAG
    14. 5.14 Test Automation Header
    15. 5.15 LIN
    16. 5.16 MMC
    17. 5.17 ADC and DAC
    18. 5.18 EQEP and SDFM
    19. 5.19 EPWM
    20. 5.20 BoosterPack Headers
    21. 5.21 Pinmux Mapping
  8. 5References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design
  9. 6Revision History

4.14 Test Automation Header

The AM263x LaunchPad supports a 40 pin test automation header that allows an external controller to manipulate basic operations such as power down, PORz, warm reset, and bootmode control.

GUID-20220502-SS0I-KGBG-9DZ2-SKTX9WF0NGVC-low.png Figure 4-17 Test Automation Header

The Test Automation Circuit is powered by a dedicated 3.3V power supply (VSYS_TA_3V3) which is generated by a 5V to 3.3V buck regulator (TPS62177DQCR).

The AM263x SoC I2C3 instance is connected to both the Test Automation Header and the bootmode IO expander (TCA6408ARGTR).

The following table details the Test Automation GPIO mapping:

Table 4-12 Test Automation GPIO Mapping
Signal Name Description Direction
TA_POWERDOWN when logic low, disables the 3.3V buck regulator (TPS62913RPUR) that is used in the first stage of DC/DC conversion Output
TA_PORZn when logic low, connects the PORz signal to ground due to the PMOS V_GS being less than zero creating a power on reset to the MAIN domain Output
TA_RESETz when logic low, connects the WARMRESETn signal to ground due to the PMOS V_GS being less than zero creating a warm reset to the MAIN domain Output
TA_GPIO1 when logic low, connects the INTn signal to ground due to the PMOS V_GS being less than zero creating an interrupt to the SoC Output
TA_GPIO2 when logic low, disables the 1.2V buck regulator (TPS62913RPUR) Output
TA_GPIO3 when logic low, disables the bootmode buffer output enable Output
TA_GPIO4 Reset signal for Bootmode IO Expander (TCA6408ARGTR) Output