SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
This register is used to configure the GPMC Clock source and Loop Back clock Source.
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| Instance Name | Physical Address |
|---|---|
| MSS_CTRL | 50D0 082Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | GPMC_CONTROL_CLK_LB_OE_N | RESERVED | GPMC_CONTROL_CLK_OE_N | ||||
| NONE | R/W | NONE | R/W | ||||
| 0h | 0h | 0h | 1h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GPMC_CONTROL_CLK_LB_SEL | RESERVED | GPMC_CONTROL_CLKOUT_SEL | ||||
| NONE | R/W | NONE | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:13 | RESERVED | NONE | 0h | Reserved |
| 12 | GPMC_CONTROL_CLK_LB_OE_N | R/W | 0h | GPMC_CLK_LB oe_n 1'b1 GPMC_dev_clk is driven to pad 1'b0 GPMC_dev_clk is not driven to pad |
| 11:9 | RESERVED | NONE | 0h | Reserved |
| 8 | GPMC_CONTROL_CLK_OE_N | R/W | 1h | GPMC_CLKOUT oe_n 1'b1 GPMC_dev_clk mux output is driven to pad 1'b0 GPMC_dev_clk mux output is not driven to pad |
| 7:5 | RESERVED | NONE | 0h | Reserved |
| 4 | GPMC_CONTROL_CLK_LB_SEL | R/W | 0h | GPMC_CLK_LB sel 1'b0 GPMC_CLK_LB pad clock 1'b1 GPMC_CLK pad clock |
| 3:1 | RESERVED | NONE | 0h | Reserved |
| 0 | GPMC_CONTROL_CLKOUT_SEL | R/W | 0h | GPMC_CLKOUT sel 1'b0 GPMC_func_clock 1'b1 GPMC_dev clock |