SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.2.7.1 MSS_TOPRCM_PLL_REF_CLK_SRC_SEL Register (Offset = 1Ch) [reset = 0h]

CORE PLL and PERI PLL reference clock select.

Table 2-1420 Instance Table

Instance Name	Physical Address
MSS_TOPRCM	5320 001Ch

Figure 2-708 MSS_TOPRCM_PLL_REF_CLK_SRC_SEL Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED
NONE
0h
15	14	13	12	11	10	9	8
RESERVED
NONE
0h
7	6	5	4	3	2	1	0
RESERVED	PLL_REF_CLK_SRC_SEL_PLL_PERI_REF_CLK_SRC_SEL			RESERVED	PLL_REF_CLK_SRC_SEL_PLL_CORE_REF_CLK_SRC_SEL
NONE	R/W			NONE	R/W
0h	0h			0h	0h

Table 2-1421 MSS_TOPRCM_PLL_REF_CLK_SRC_SEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:7	RESERVED	NONE	0h	Reserved
6:4	PLL_REF_CLK_SRC_SEL_PLL_PERI_REF_CLK_SRC_SEL	R/W	0h	Mux selct for PERI PLL REF clock Write 3'b111 : to select external reference clock as PLL reference clock Write 3'b000 : to select XTAL clock as PLL reference clock
3	RESERVED	NONE	0h	Reserved
2:0	PLL_REF_CLK_SRC_SEL_PLL_CORE_REF_CLK_SRC_SEL	R/W	0h	Mux selct for CORE PLL REF clock Write 3'b111 : to select external reference clock as PLL reference clock Write 3'b000 : to select XTAL clock as PLL reference clock