SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.5.2.78 MSS_TOPRCM_HW_SPARE_REC Register

5.2.78.1 MSS_TOPRCM_HW_SPARE_REC Register (Offset = FF4h) [reset = 0h]

HW_SPARE_REC.

Table 2-1562 Instance Table

Instance Name	Physical Address
MSS_TOPRCM	5320 0FF4h

Figure 2-779 MSS_TOPRCM_HW_SPARE_REC Name Register

31	30	29	28	27	26	25	24
HW_SPARE_REC_HW_SPARE_REC31	HW_SPARE_REC_HW_SPARE_REC30	HW_SPARE_REC_HW_SPARE_REC29	HW_SPARE_REC_HW_SPARE_REC28	HW_SPARE_REC_HW_SPARE_REC27	HW_SPARE_REC_HW_SPARE_REC26	HW_SPARE_REC_HW_SPARE_REC25	HW_SPARE_REC_HW_SPARE_REC24
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
23	22	21	20	19	18	17	16
HW_SPARE_REC_HW_SPARE_REC23	HW_SPARE_REC_HW_SPARE_REC22	HW_SPARE_REC_HW_SPARE_REC21	HW_SPARE_REC_HW_SPARE_REC20	HW_SPARE_REC_HW_SPARE_REC19	HW_SPARE_REC_HW_SPARE_REC18	HW_SPARE_REC_HW_SPARE_REC17	HW_SPARE_REC_HW_SPARE_REC16
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
15	14	13	12	11	10	9	8
HW_SPARE_REC_HW_SPARE_REC15	HW_SPARE_REC_HW_SPARE_REC14	HW_SPARE_REC_HW_SPARE_REC13	HW_SPARE_REC_HW_SPARE_REC12	HW_SPARE_REC_HW_SPARE_REC11	HW_SPARE_REC_HW_SPARE_REC10	HW_SPARE_REC_HW_SPARE_REC9	HW_SPARE_REC_HW_SPARE_REC8
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
HW_SPARE_REC_HW_SPARE_REC7	HW_SPARE_REC_HW_SPARE_REC6	HW_SPARE_REC_HW_SPARE_REC5	HW_SPARE_REC_HW_SPARE_REC4	HW_SPARE_REC_HW_SPARE_REC3	HW_SPARE_REC_HW_SPARE_REC2	HW_SPARE_REC_HW_SPARE_REC1	HW_SPARE_REC_HW_SPARE_REC0
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 2-1563 MSS_TOPRCM_HW_SPARE_REC Register Field Descriptions

Bit	Field	Type	Reset	Description
31	HW_SPARE_REC_HW_SPARE_REC31	R/W	0h	Reserved for HW R&D
30	HW_SPARE_REC_HW_SPARE_REC30	R/W	0h	Reserved for HW R&D
29	HW_SPARE_REC_HW_SPARE_REC29	R/W	0h	Reserved for HW R&D
28	HW_SPARE_REC_HW_SPARE_REC28	R/W	0h	Reserved for HW R&D
27	HW_SPARE_REC_HW_SPARE_REC27	R/W	0h	Reserved for HW R&D
26	HW_SPARE_REC_HW_SPARE_REC26	R/W	0h	Reserved for HW R&D
25	HW_SPARE_REC_HW_SPARE_REC25	R/W	0h	Reserved for HW R&D
24	HW_SPARE_REC_HW_SPARE_REC24	R/W	0h	Reserved for HW R&D
23	HW_SPARE_REC_HW_SPARE_REC23	R/W	0h	Reserved for HW R&D
22	HW_SPARE_REC_HW_SPARE_REC22	R/W	0h	Reserved for HW R&D
21	HW_SPARE_REC_HW_SPARE_REC21	R/W	0h	Reserved for HW R&D
20	HW_SPARE_REC_HW_SPARE_REC20	R/W	0h	Reserved for HW R&D
19	HW_SPARE_REC_HW_SPARE_REC19	R/W	0h	Reserved for HW R&D
18	HW_SPARE_REC_HW_SPARE_REC18	R/W	0h	Reserved for HW R&D
17	HW_SPARE_REC_HW_SPARE_REC17	R/W	0h	Reserved for HW R&D
16	HW_SPARE_REC_HW_SPARE_REC16	R/W	0h	Reserved for HW R&D
15	HW_SPARE_REC_HW_SPARE_REC15	R/W	0h	Reserved for HW R&D
14	HW_SPARE_REC_HW_SPARE_REC14	R/W	0h	Reserved for HW R&D
13	HW_SPARE_REC_HW_SPARE_REC13	R/W	0h	Reserved for HW R&D
12	HW_SPARE_REC_HW_SPARE_REC12	R/W	0h	Reserved for HW R&D
11	HW_SPARE_REC_HW_SPARE_REC11	R/W	0h	Reserved for HW R&D
10	HW_SPARE_REC_HW_SPARE_REC10	R/W	0h	Reserved for HW R&D
9	HW_SPARE_REC_HW_SPARE_REC9	R/W	0h	Reserved for HW R&D
8	HW_SPARE_REC_HW_SPARE_REC8	R/W	0h	Reserved for HW R&D
7	HW_SPARE_REC_HW_SPARE_REC7	R/W	0h	Reserved for HW R&D
6	HW_SPARE_REC_HW_SPARE_REC6	R/W	0h	Reserved for HW R&D
5	HW_SPARE_REC_HW_SPARE_REC5	R/W	0h	Reserved for HW R&D
4	HW_SPARE_REC_HW_SPARE_REC4	R/W	0h	Reserved for HW R&D
3	HW_SPARE_REC_HW_SPARE_REC3	R/W	0h	Reserved for HW R&D
2	HW_SPARE_REC_HW_SPARE_REC2	R/W	0h	Reserved for HW R&D
1	HW_SPARE_REC_HW_SPARE_REC1	R/W	0h	Reserved for HW R&D
0	HW_SPARE_REC_HW_SPARE_REC0	R/W	0h	Reserved for HW R&D