SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.2.39.1 TOP_CTRL_TSENSE1_CNTL Register (Offset = D48h) [reset = 100000h]

This register is used to control and configure Temperature sensor 1

Table 2-1006 Instance Table

Instance Name	Physical Address
TOP_CTRL	50D8 0D48h

Figure 2-502 TOP_CTRL_TSENSE1_CNTL Name Register

Table 2-1007 TOP_CTRL_TSENSE1_CNTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:25	RESERVED	NONE	0h	Reserved
24	TSENSE1_CNTL_MASK_LOW_THRHLD	R/W	0h	mask low threshold comparator output **Note: This bit will only be reset by PORz.
23:21	RESERVED	NONE	0h	Reserved
20	TSENSE1_CNTL_MASK_COLD	R/W	1h	Mask hot comparator output **Note: This bit will only be reset by PORz.
19:17	RESERVED	NONE	0h	Reserved
16	TSENSE1_CNTL_MASK_HOT	R/W	0h	mask cold comparator output **Note: This bit will only be reset by PORz.
15:9	RESERVED	NONE	0h	Reserved
8	TSENSE1_CNTL_ACCU_CLEAR	R/W	0h	Accumulator clear **Note: This bit will only be reset by PORz.
7:5	RESERVED	NONE	0h	Reserved
4	TSENSE1_CNTL_FIFO_FREEZE	R/W	0h	fifo freeze **Note: This bit will only be reset by PORz.
3:1	RESERVED	NONE	0h	Reserved
0	TSENSE1_CNTL_FIFO_CLEAR	R/W	0h	fifo clear **Note: This bit will only be reset by PORz.