SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.2.2.63 ADC_CFG_ADCSOC2CTL Register

2.2.63.1 ADC_CFG_ADCSOC2CTL Register (Offset = 28h) [reset = 0h]

ADC SOC2 Control Register.

Table 3-129 Instance Table

Instance Name	Physical Address
ADC0_G0_G5	502C 0028h
ADC1_G0_G5	502C 1028h
ADC2_G0_G5	502C 2028h
ADC3_G0_G5	502C 3028h
ADC4_G0_G5	502C 4028h

Figure 3-63 ADC_CFG_ADCSOC2CTL Name Register

31	30	29	28	27	26	25	24
EXTCHSEL				RESERVED_2	TRIGSEL
R/W				R	R/W
0h				0h	0h
23	22	21	20	19	18	17	16
TRIGSEL				CHSEL
R/W				R/W
0h				0h
15	14	13	12	11	10	9	8
CHSEL	RESOLUTION			SIGNALMODE		RESERVED_1	ACQPS
R/W	R			R		R	R/W
0h	0h			0h		0h	0h
7	6	5	4	3	2	1	0
ACQPS
R/W
0h

Table 3-130 ADC_CFG_ADCSOC2CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:28	EXTCHSEL	R/W	0h	SOC2 External Channel Mux Select. Selects the external mux combination to output when SOC2 is received by the ADC. Some or all of the ADCEXTMUX lines can be enabled via the device GPIO mux to control an external analog mux.
27	RESERVED_2	R	0h	Reserved
26:20	TRIGSEL	R/W	0h	SOC2 Trigger Source Select. Along with the SOC2 field in the ADCINTSOCSEL1 register, this bit field configures which trigger will set the SOC2 flag in the ADCSOCFLG1 register to initiate a conversion to start once priority is given to it. Note: SOCFRC1 register can always be used to software trigger SOCs in addition to any hardware trigger configuration. 00h ADCTRIG0 - Software only 01h ADCTRIG1 - RTI0 Timer 02h ADCTRIG2 - RTI1 Timer 03h ADCTRIG3 - RTI2 Timer 04h ADCTRIG4 - RTI3 Timer 05h ADCTRIG5 - InputXBAR.Out[5] 06h ADCTRIG6 - spare 07h ADCTRIG7 - spare 08h ADCTRIG8 - EPWM0, ADCSOCA 09h ADCTRIG9 - EPWM0, ADCSOCB 0Ah ADCTRIG10 - EPWM1, ADCSOCA 0Bh ADCTRIG11 - EPWM1, ADCSOCB 0Ch ADCTRIG12 - EPWM2, ADCSOCA 0Dh ADCTRIG13 - EPWM2, ADCSOCB 0Eh ADCTRIG14 - EPWM3, ADCSOCA 0Fh ADCTRIG15 - EPWM3, ADCSOCB .... EPWM4 to EPWM27 40h ADCTRIG64 - EPWM28, ADCSOCA 41h ADCTRIG65 - EPWM28, ADCSOCB 42h ADCTRIG66 - EPWM29, ADCSOCA 43h ADCTRIG67 - EPWM29, ADCSOCB 44h ADCTRIG68 - EPWM30, ADCSOCA 45h ADCTRIG69 - EPWM30, ADCSOCB 46h ADCTRIG70 - EPWM31, ADCSOCA 47h ADCTRIG71 - EPWM31, ADCSOCB 48h ADCTRIG72 - ECAP0, TRIGOUT .... ECAP1 to ECAP8 51h ADCTRIG81 - ECAP9, TRIGOUT 52h ADCTRIG82 - ECAP10, TRIGOUT .... 57h ADCTRIG87 - ECAP15, TRIGOUT 58h ADCTRIG88 - RTI4 Timer 59h ADCTRIG89 - RTI5 Timer 5Ah ADCTRIG90 - RTI6 Timer 5Bh ADCTRIG91 - RTI7 Timer .... 7Eh ADCTRIG126 - REP1TRIG - these are not external trigger signals on the ADC IP port. We need to configure them for internal selection of repeater triggers. 7Fh ADCTRIG127 - REP2TRIG - these are not external trigger signals on the ADC IP port. We need to configure them for internal selection of repeater triggers.
19:15	CHSEL	R/W	0h	SOC2 Channel Select. Selects the channel to be converted when SOC2 is received by the ADC. Single-ended Signaling Mode [SIGNALMODE = 0]: 00h ADCIN0 01h ADCIN1 02h ADCIN2 03h ADCIN3 ... 1Dh ADCIN29 1Eh ADCIN30 1Fh ADCIN31 Differential Signaling Mode [SIGNALMODE = 1]: 00h ADCIN0 [non-inverting] and ADCIN1 [inverting] 01h ADCIN0 [non-inverting] and ADCIN1 [inverting] 02h ADCIN2 [non-inverting] and ADCIN3 [inverting] 03h ADCIN2 [non-inverting] and ADCIN3 [inverting] 04h ADCIN4 [non-inverting] and ADCIN5 [inverting] 05h ADCIN4 [non-inverting] and ADCIN5 [inverting] ... 0Eh ADCIN26 [non-inverting] and ADCIN27 [inverting] 0Fh ADCIN26 [non-inverting] and ADCIN27 [inverting] 10h ADCIN28 [non-inverting] and ADCIN29 [inverting] 11h ADCIN28 [non-inverting] and ADCIN29 [inverting] 1Eh ADCIN30 [non-inverting] and ADCIN31 [inverting] 1Fh ADCIN30 [non-inverting] and ADCIN31 [inverting]
14:12	RESOLUTION	R	0h	Placeholder for per-SOC resolution
11:10	SIGNALMODE	R	0h	Placeholder for per-SOC signal mode
9	RESERVED_1	R	0h	Reserved
8:0	ACQPS	R/W	0h	SOC2 Acquisition Prescale. Controls the sample and hold window for this SOC. 000h Reserved 001h Reserved 002h Sample window is 3 system clock cycles wide 003h Sample window is 4 system clock cycles wide ... 1FFh Sample window is 512 system clock cycles wide The configured acquisition time must be at least as long as one ADCCLK cycle for correct ADC operation. The configured acquisition time must also be at least 3 SYSCLK cycles long. The device datasheet will also specify a minimum sample and hold window duration.