SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

12.2.30.1 CFG_ECR Register (Offset = 240h) [reset = 0h]

Error Counter Register. State of Rx/Tx Error counter, CAN error logging.

Table 5-1432 Instance Table

Figure 5-706 CFG_ECR Name Register

Table 5-1433 CFG_ECR Register Field Descriptions

Bit	Field	Type	Reset	Description
31:24	NU25	R	0h	Reserved
23:16	CEL	R	0h	CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented. It is reset by read access to the MCAN_ECR[23-16] CEL field. The counter stops at FFh; the next increment of the MCAN_ECR[7-0] TEC or MCAN_ECR[14-8] REC fields sets interrupt flag MCAN_IR[22] ELO.
15	RP	R	0h	Recieve Error Passive 1'b0 = The Receive Error Counter is below the error passive level of 128 1'b1 = The Receive Error Counter has reached the error passive level of 128
14:8	REC	R	0h	Recieve Error Counter Actual state of the Receive Error Counter, values between 0 and 127.
7:0	TEC	R	0h	Transmit Error Counter Actual state of the Transmit Error Counter, values between 0 and 255. Note: When the MCAN_CCCR[2] ASM bit is set, the CAN protocol controller does not increment the MCAN_ECR[7-0] TEC and MCAN_ECR[14-8] REC fields when a CAN protocol error is detected, but the MCAN_ECR[23-16] CEL field is still incremented.