SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Interrupt Enable Register. The settings in the Interrupt Enable register determine which status changes in the MCAN_IR register are signalled on an interrupt line.
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| Instance Name | Physical Address |
|---|---|
| MCAN0 | 5260 8254h |
| MCAN1 | 5261 8254h |
| MCAN2 | 5262 8254h |
| MCAN3 | 5263 8254h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| NU31 | ARAE | PEDE | PEAE | WDIE | BOE | EWE | |
| R | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| EPE | ELOE | BEUE | BECE | DRX | TOOE | MRAFE | TSWE |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TEFLE | TEFFE | TEFWE | TEFNE | TFEE | TCFE | TCE | HPME |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RF1LE | RF1FE | RF1WE | RF1NE | RF0LE | RF0FE | RF0WE | RF0NE |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | NU31 | R | 0h | Reserved |
| 29 | ARAE | R/W | 0h | Accees to Reserve Address Interrupt Enable |
| 28 | PEDE | R/W | 0h | Protocol Error in Data Phase Interrupt Enable |
| 27 | PEAE | R/W | 0h | Protocol Error in Arbitration Phase Interrupt Enable |
| 26 | WDIE | R/W | 0h | Watchdog Interrupt Enable |
| 25 | BOE | R/W | 0h | Bus_Off Status Interrupt Enable |
| 24 | EWE | R/W | 0h | Warning Status Interrupt Enable |
| 23 | EPE | R/W | 0h | Error Passive Interrupt Enable |
| 22 | ELOE | R/W | 0h | Error Logging Overflow Interrupt Enable |
| 21 | BEUE | R/W | 0h | Bit Error Uncorrected Interrupt Enable |
| 20 | BECE | R/W | 0h | Bit Error Corrected Interrupt Enable |
| 19 | DRX | R/W | 0h | Message stored to Dedicated Rx Buffer Interrupt Enable |
| 18 | TOOE | R/W | 0h | Timeout Occurred Interrupt Enable |
| 17 | MRAFE | R/W | 0h | Message RAM Access Failure Interrupt Enable |
| 16 | TSWE | R/W | 0h | Timestamp Wraparound Interrupt Enable |
| 15 | TEFLE | R/W | 0h | Tx Event FIFO Event Lost Interrupt Enable |
| 14 | TEFFE | R/W | 0h | Tx Event FIFO Full Interrupt Enable |
| 13 | TEFWE | R/W | 0h | Tx Event FIFO Watermark Reached Interrupt enable |
| 12 | TEFNE | R/W | 0h | Tx Event FIFO New Entry Interrupt Enable |
| 11 | TFEE | R/W | 0h | Tx FIFO Empty Interrupt Enable |
| 10 | TCFE | R/W | 0h | Transmission Cancellation Finishied Interrupt Enable |
| 9 | TCE | R/W | 0h | Transmission Completed Interrupt Enable |
| 8 | HPME | R/W | 0h | High Priority message Interrupt Enable |
| 7 | RF1LE | R/W | 0h | Rx FIFO 1 Message Lost Interrupt Enable |
| 6 | RF1FE | R/W | 0h | Rx FIFO 1 Full Interrupt Enable |
| 5 | RF1WE | R/W | 0h | Rx FIFO 1 Watermark Reached Interrupt Enable |
| 4 | RF1NE | R/W | 0h | Rx FIFO 1 New Message Interrupt Enable |
| 3 | RF0LE | R/W | 0h | Rx FIFO 0 Message Lost Interrupt Enable |
| 2 | RF0FE | R/W | 0h | Rx FIFO 0 Full Interrupt Enable |
| 1 | RF0WE | R/W | 0h | Rx FIFO 0 Watermark Reached Interrupt Enable |
| 0 | RF0NE | R/W | 0h | Rx FIFO 0 New Message Interrupt Enable |