SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

12.2.55.1 CFG_RXF0S Register (Offset = 2A4h) [reset = 0h]

Rx FIFO 0 Status register. FIFO 0 message lost/full indication, put index, get index and fill level.

Table 5-1482 Instance Table

Figure 5-731 CFG_RXF0S Name Register

Table 5-1483 CFG_RXF0S Register Field Descriptions

Bit	Field	Type	Reset	Description
31:26	NU46	R	0h	Reserved
25	RF0L	R	0h	Rx FIFO 0 Message Lost This bit is a copy of interrupt flag MCAN_IR[3] RF0L. When the MCAN_IR[3] RF0L flag is reset, this bit is also reset. 1'b0 = No Rx FIFO 0 message lost 1'b1 = Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero Note: OverWriting the oldest message when the MCAN_RXF0C[31] F0OM = 1'b1 will not set this flag.
24	F0F	R	0h	Rx FIFO 0 Full
23:22	NU45	R	0h	Reserved
21:16	F0PI	R	0h	Rx FIFO 0 Put Index
15:14	NU44	R	0h	Reserved
13:8	F0GI	R	0h	Rx FIFO 0 Get Index
7	NU43	R	0h	Reserved
6:0	F0FL	R	0h	Rx FIFO 0 Fill Level