SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

12.2.56.1 CFG_RXF0A Register (Offset = 2A8h) [reset = 0h]

Rx FIFO 0 Acknowledge register. FIFO 0 acknowledge last index of read buffers, updates get index and fill level.

Table 5-1484 Instance Table

Figure 5-732 CFG_RXF0A Name Register

Table 5-1485 CFG_RXF0A Register Field Descriptions

Bit	Field	Type	Reset	Description
31:6	NU47	R	0h	Reserved
5:0	F0AI	R/W	0h	Rx FIFO 0 Acknowledge Index After the Host CPU has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to the MCAN_RXF0A[5-0] F0AI field. This will set the Rx FIFO 0 Get Index MCAN_RXF0S[13-8] F0GI field to the MCAN_RXF0A[5-0] F0AI field + 1 and update the FIFO 0 Fill Level MCAN_RXF0S[6-0] F0FL field.