SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.9.2.2 FSI_RX_CFG_RX_OPER_CTRL Register

9.2.2.1 FSI_RX_CFG_RX_OPER_CTRL Register (Offset = 8h) [reset = 0h]

Receive operation control register.

Table 3-996 Instance Table

Instance Name	Physical Address
FSI_RX0	5029 0008h
FSI_RX1	5029 1008h
FSI_RX2	502B 0008h
FSI_RX3	502B 1008h

Figure 3-467 FSI_RX_CFG_RX_OPER_CTRL Name Register

15	14	13	12	11	10	9	8
RESERVED_1							PING_WD_RST_MODE
R							R/W
0h							0h
7	6	5	4	3	2	1	0
ECC_SEL	N_WORDS				SPI_MODE	DATA_WIDTH
R/W	R/W				R/W	R/W
0h	0h				0h	0h

Table 3-997 FSI_RX_CFG_RX_OPER_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
15:9	RESERVED_1	R	0h	Reserved
8	PING_WD_RST_MODE	R/W	0h	Ping Watchdog Timeout Mode Select bit This bit selects the mode by which the ping watchdog counter is reset. The watchdog counter can be reset and restarted only by ping frames or by any received frame. 0h[R/W] = The ping watchdog counter will reset and restart only by ping frames. 1h[R/W] = The ping watchdog counter will reset and restart by any received frame.
7	ECC_SEL	R/W	0h	ECC Data Width Select bit This bit selects between whether the ECC computation is done on 16-bit or 32-bit words. 0h[R/W] = 32-bit ECC is used. 1h[R/W] = 16-bit ECC is used.
6:3	N_WORDS	R/W	0h	Number of Words to Receive This field defines the number of words which will be received in a DATA_N_WORD frame. This is a user-defined field that must match the corresponding field in the transmitter. Set this bitfield to be one less than the number of words to be received. This value is only applicable when the frame type received is DATA_N_WORD. 0h[R/W] = 1 data word frame [16-bit data]. 1h[R/W] = 2 data word frame [32-bit data]. .. Fh [R/W] = 16 data word frame [256-bit data].
2	SPI_MODE	R/W	0h	SPI Mode Enable bit This bit enables and disables the SPI compatibility mode of the FSI RX. The received data must be formatted as an FSI frame in order for the data to properly be received. SPI compatibility mode will allow FSI RX to receive data that is sent using SPI signal format. Refer to the applicable section in the FSI TRM chapter for more information. 0h[R/W] = FSI is in normal mode of operation. 1h[R/W] = FSI is operating in SPI compatibility mode.
1:0	DATA_WIDTH	R/W	0h	Receive Data Width Select bit These bits decide the number of data lines used for receiving data. 0h[R/W] = Data will be received on one data line, RXD0. 1h[R/W] = Data will be received on two data lines, RXD0 and RXD1. 2h 3h[R/W] = Reserved