SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Datalogger 0 .
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| Instance Name | Physical Address |
|---|---|
| PBIST0 | 5330 0164h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DLR1 | |||||||
| R/W | |||||||
| 2h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DLR0 | |||||||
| R/W | |||||||
| 8h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:8 | DLR1 | R/W | 2h | Datalogger Register [8] : Reserevd [9] : Default Testing Mode. When in this mode, ROM-based testing is kicked off. If the intention is to perform go/no-go testing via config, write to both this bit and bit [2] of the Datalogger Register simultaneously [15:10] : Reserevd |
| 7:0 | DLR0 | R/W | 8h | Datalogger Register [1:0] : Reserved [2] : ROM-based testing mode. Setting this bit to 1 enables the PBIST controller to execute test algorithms that are stored in the PBIST ROM [3] : Do not change this bit from its default value of 1 [4] : Config access mode. Setting this bit allows the host processor to configure the PBIST controller registers [7:5] : Reserved |