SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.25.2.1 WDT_RTIGCTRL Register

25.2.1.1 WDT_RTIGCTRL Register (Offset = 0h) [reset = 0h]

Global Control Register starts / stops the counters .

Table 5-2405 Instance Table

Instance Name	Physical Address
WDT0	5210 0000h
WDT1	5210 1000h
WDT2	5210 2000h
WDT3	5210 3000h

Figure 5-1182 WDT_RTIGCTRL Name Register

31	30	29	28	27	26	25	24
RESERVED2
R/W
0h
23	22	21	20	19	18	17	16
RESERVED2				NTUSEL
R/W				R/W
0h				0h
15	14	13	12	11	10	9	8
COS	RESERVED1
R/W	R/W
0h	0h
7	6	5	4	3	2	1	0
RESERVED1						CNT1EN	CNT0EN
R/W						R/W	R/W
0h						0h	0h

Table 5-2406 WDT_RTIGCTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:20	RESERVED2	R/W	0h	Reserved. Reads return 0 and writes have no effect
19:16	NTUSEL	R/W	0h	NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being used as the NTU signal. The NTU signal will also be TIED LOW in case of a single-bit flip as it will result in an invalid combination of NTUSEL. User and privilege mode [read]: 0000= NTU0 0101= NTU1 1010= NTU2 1111= NTU3 other = tied to 0 Privilege mode [write]: 0000= NTU0 0101= NTU1 1010= NTU2 1111= NTU3 other = tied to 0
15	COS	R/W	0h	COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode [read]: 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode [write]: 0 = stop counters in debug mode 1 = continue counting in debug mode
14:2	RESERVED1	R/W	0h	Reserved. Reads return 0 and writes have no effect
1	CNT1EN	R/W	0h	CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 [UC1 and FRC1]. User and privilege mode [read]: 0 = counters are stopped 1 = counters are running Privilege mode [write]: 0 = stop counters 1 = start counters Gives the absolute 32 bit destination address [physical].
0	CNT0EN	R/W	0h	CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 [UC0 and FRC0]. User and privilege mode [read]: 0 = counters are stopped 1 = counters are running Privilege mode [write]: 0 = stop counters 1 = start counters Gives the absolute 32 bits source address [physical].